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Rochester Electronics LLC 74LVX112SJ IC FF JK TYPE DUAL 1BIT 16SOP
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	74LVX112SJ	Tube			1,268	1 - 10 - 100 - 1000 - 10000 $0.24	Buy Now
Rochester Electronics LLC 74LVX112MTC IC FF JK TYPE DUAL 1BIT 16TSSOP
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	74LVX112MTC	Tube			2,049	1 - 10 - 100 - 1000 - 10000 $0.15	Buy Now
onsemi 74LVX112MTC IC FF JK TYPE DUAL 1BIT 16TSSOP
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	74LVX112MTC	Tube			2,350	1 - 10 - 100 - 1000 - 10000 $0.30407	Buy Now
Rochester Electronics LLC 74LVX112MTCX IC FF JK TYPE DUAL 1BIT 16TSSOP
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	74LVX112MTCX	Bulk			2,049	1 - 10 - 100 - 1000 - 10000 $0.15	Buy Now
Fairchild Semiconductor Corporation 74LVX112MTC J-K Flip-Flop, LV/LV-A/LVX/H Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16 '
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Rochester Electronics	74LVX112MTC		8,336		1	1 $0.1408 10 $0.1408 100 $0.1324 1000 $0.1197 10000 $0.1197	Buy Now

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LVX112 Datasheets (1)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
LVX112		National Semiconductor	Low Voltage Dual J-K Flip-Flops with Preset and Clear		Original	PDF

LVX112 Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
74LVX112 Abstract: 74LVX112M 74LVX112MTC 74LVX112SJ LVX112 M16A M16D MTC16 Text: LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear General Description The LVX112 is a dual J-K Flip-Flop where each flip-flop has independent inputs J, K, PRESET, CLEAR, and CLOCK and outputs (Q, Q). These devices are edge sensitive and change states synchronously on the negative going transition of the clock pulse. Triggering occurs at a voltage level of	Original	PDF	74LVX112 LVX112 74LVX112 74LVX112M 74LVX112MTC 74LVX112SJ M16A M16D MTC16
74LVX112 Abstract: 74LVX112M 74LVX112MTC 74LVX112SJ LVX112 M16A M16D MTC16 Text: Revised December 2003 LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear General Description The LVX112 is a dual J-K Flip-Flop where each flip-flop has independent inputs J, K, PRESET, CLEAR, and CLOCK and outputs (Q, Q). These devices are edge sensitive and	Original	PDF	74LVX112 LVX112 74LVX112 74LVX112M 74LVX112MTC 74LVX112SJ M16A M16D MTC16
LVX165 Abstract: MC74LVX3245 lvx161284 lvx125 lvx245 LVX132 MC74LVX2 LVX541 74lv139 applications hex inverter Text: HC Portfolio Comparison PART # LVX00 LVX02 LVX04 LVXU04 LVX05 LVX06 LVX07 LVX08 LVX10 LVX11 LVX14 LVX20 LVX21 LVX27 LVX32 LVX50 LVX74 LVX86 LVX107 LVX109 LVX112 LVX123 LVX125 LVX126 LVX132 LVX138 LVX139 LVX153 LVX154 LVX157 LVX158 LVX161 LVX163 LVX164 LVX165	Original	PDF	LVX00 LVX02 LVX04 LVXU04 LVX05 LVX06 LVX07 LVX08 LVX10 LVX11 LVX165 MC74LVX3245 lvx161284 lvx125 lvx245 LVX132 MC74LVX2 LVX541 74lv139 applications hex inverter
74LVX112 Abstract: 74LVX112M 74LVX112MTC 74LVX112MTCX 74LVX112MX 74LVX112SJ 74LVX112SJX LVX112 M16A M16D Text: LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear General Description The LVX112 is a dual J-K Flip-Flop where each flip-flop has independent inputs J K PRESET CLEAR and CLOCK and outputs (Q Q) These devices are edge sensitive and change states synchronously on the negative going transition of the clock pulse Triggering occurs at a voltage level	Original	PDF	74LVX112 LVX112 74LVX112 74LVX112M 74LVX112MTC 74LVX112MTCX 74LVX112MX 74LVX112SJ 74LVX112SJX M16A M16D
74LVX112 Abstract: 74LVX112M 74LVX112MTC 74LVX112SJ LVX112 M16A M16D MTC16 Text: Revised March 1999 LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear General Description The LVX112 is a dual J-K Flip-Flop where each flip-flop has independent inputs J, K, PRESET, CLEAR, and CLOCK and outputs (Q, Q). These devices are edge sensitive and	Original	PDF	74LVX112 LVX112 74LVX112 74LVX112M 74LVX112MTC 74LVX112SJ M16A M16D MTC16
Untitled Abstract: No abstract text available Text: S E M IC O N D U C T O R LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear General Description Th e inputs tolerate voltages up to 7V allowing the interface of 5V system s to 3V system s. The LVX112 is a dual J-K Flip-Flop where each flip-flop has	OCR Scan	PDF	74LVX112 LVX112 2314-006I
MTC 25-16 Abstract: 74LVX112 74LVX112M 74LVX112MTC 74LVX112SJ LVX112 M16A M16D MTC16 Text: A I R C H I I- D S E M IC O N D U C T O R im LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear General Description The inputs tolerate voltages up to 7 V allowing the interface of 5V system s to 3 V system s. The LVX112 is a dual J-K Flip-Flop w here each flip-flop has	OCR Scan	PDF	74LVX112 LVX112 MTC 25-16 74LVX112 74LVX112M 74LVX112MTC 74LVX112SJ M16A M16D MTC16
Untitled Abstract: No abstract text available Text: A I R C H October 1996 I L D Revised March 1999 S E M [CONDUCTOR TM LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear General Description The LVX112 is a dual J-K Flip-Flop where each flip-flop has independent inputs J, K, PRESET, CLEAR, and CLOCK	OCR Scan	PDF	74LVX112 LVX112
Untitled Abstract: No abstract text available Text: Revised March 1999 SEMICONDUCTOR TM General Description The inputs tolerate voltages up to 7V allowing the interface of 5V system s to 3V system s. Features • Input voltage level translation from 5 V -3 V ■ Ideal fo r low pow er/low noise 3.3V applications	OCR Scan	PDF	74LVX112 74LVX112 LVX112
74LVX112 Abstract: 74LVX112M 74LVX112MTC 74LVX112SJ LVX112 M16A M16D MTC16 AD508 Text: S E M I C O N D U C T O R Revised March 1999 TM General Description either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. The inputs tolerate voltages up to 7V allowing the interface	OCR Scan	PDF	74LVX112 LVX112 74LVX112 74LVX112M 74LVX112MTC 74LVX112SJ M16A M16D MTC16 AD508