84PIN Search Results

Contextual Info: S2PIN 84PIN -2.0* no.of c o n ta c ts -1 ±0.15- REV. LD CN i- 2 .0 D E S C R IP T IO N DATE NOTE: Material: m ousing: Polyester, UL94V-0. 2.Terminal: Copper alloy. Gold-plated. 00u Electrical: 1. Current rating: 2 Amp. 2. Contact resistance: 30mft Max.

WE-DSP16

Abstract: wedsp16
Contextual Info: Preliminary Data Sheet WE DSP16 Digital Signal Processor Description The WEDSP16 Digital Signal Processor is a 16-bit high-speed programmable integrated circuit. The device is fabricated in low-power CMOS technology. The standard DSP16 device described in this data sheet is packaged in an 84pin plastic leaded chip carrier. A military version

JEDEC MO 047AF

Abstract: QFJ84-P-S115-1 HE 301 EE-54
Contextual Info: 84P0 Plastic 84pin QFJ EIAJ Package Code QFJ84-P-S115-1.27 JEDEC Code MO-047AF Weight g 6.49 Lead Material Alloy 42 e1 D e HD D 1 84 75 12 b2 11 e1 E L 74 I1 I2 e1 E E 54 32 33 53 A1 b1 c HE Recommended Mount Pad A b e e1 D y Symbol A A1 b b1 c D E e e1D

Contextual Info: Advance Data Sheet WE DSP16A Digital Signal Processor Description The WE DSP16A Digital Signal Processor is a 16-bit high-speed programmable integrated circuit. The device is fabricated in low-power CMOS technology and is packaged in an 84pin plastic leaded chip carrier. The DSP16A

74HC612

Contextual Info: UIV1C UM82C286 MËÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊÊËÊÊÊÊKÊÊÊBBBËHÈ P C /A T C om patible Wêêêêêêêêêêêêêêêêêêêêêêêêêêêêêêêêêêêê Chip S e t F eatures • 100% hardware and software compatible w ith the IBM PC/AT

er36 transformer

Contextual Info: S TANDARD PRO DUCT PM PMC-Sierra, inc. PM 7345 S/UNI-PDH ISSUE 5 SATURN User Network Interface forPD H PM7345 S/UNI- fTM PDH S/UNI-PDH S A T U R N U s e r N e t w o r k I n t e r f a c e for A T M P l e s i o c h r o n o u s Di gi t al H i e r a r c h y Pre lim ina ry

diode p4e

Contextual Info: TLC34058 256 x 24 COLOR PALETTE SLAS050 – D3961, NOVEMBER 1991 • • • • • • • • LinEPIC 1-µm CMOS Process 125-MHz Pipelined Architecture Available Clock Rates . . . 80, 110, 125, 135 MHz Dual-Port Color RAM 256 Words x 24 Bits Bit Plane Read and Blink Masks

8251a usart interface from z80

Abstract: UDL TM 500 f922 verilog code for 8254 timer l912 256x32 POWER MODULE TM 31 udl 500 78K3 F5S4
Contextual Info: L4E75BS DÜHBÖGb 3ÔÔ B I N E C E CB-C7, 5-VOLT 0.8-M ICRON CELL-BASED CMOS ASIC NEC NEC Electronics Inc. August 1993 Description Figure 1. Integrated HDD Solution with CBC7 Cell-Based ASIC with Embedded 78K3 MPU, Compiled SRAMs and A/D Converters CB-C7 cell-based product family is a 0.8-micron drawn

vq80

Abstract: A40MX02 one time
Contextual Info: Revision 3 40MX and 42MX Automotive FPGA Families Features High Capacity Ease of Integration • Single-Chip Applications ASIC Alternative for Automotive • Up to 100% Resource Utilization and 100% Pin Locking • 3,000 to 54,000 System Gates • Deterministic, User-Controllable Timing

MT90812AL1

Abstract: TGE-5 EB32
Contextual Info: MT90812 Integrated Digital Switch IDX Advance Information Mar 2011 Features • • • • • • • • • • • • • • • • • • MT90812AP MT90812AL MT90812APR MT90812AP1 MT90812AL1 MT90812APR1 192 channel x 192 channel non-blocking switching

Contextual Info: SM803xxx Flexible Ultra-Low Jitter Clock Synthesizer ClockworksTM FLEX2 General Description The SM803xxx is a dual PLL clock generator that achieves ultra-low, 75fs RMS phase jitter. With 12 total outputs and dividers on each output, this device can generate 12 different frequencies up to 850MHz. It accepts

AC162049

Abstract: AC244033 rj11 6pin pinout AC244028 PIC12F510 memory programming PIC24F16KA101 AC244023 AC162061 PIC18F14K50-ICE PIC12F675-ICD
Contextual Info: Header Board Specification WHY DO I NEED A HEADER TO DEBUG? Some PIC microcontrollers, particularly low pin count devices with 20 pins or less , generally must use a header for debugging. This is done to free up I/O lines for your application and to make production parts more affordable. Optional headers are also

EPF10K70

Abstract: EPM7128S 6 pin mini-din connector EPF10K20 9 pin mini-din monitor connector moving message display using 7 segment EPC1P1 EPM7128* kit EPM7128S Application
Contextual Info: December 2004, v3.1 Introduction University Program UP2 Education Kit User Guide The University Program UP2 Education Kit was designed to meet the needs of universities teaching digital logic design with state-of-the-art development tools and programmable logic devices PLDs . The package

s3c2440 pin

Abstract: S3C2440A s3c2440A ARM920T S3C2440 Samsung S3C2440 samsung s3c2440 arm920t core TSXP ARM920T EINT20 128MBYTE
Contextual Info: Embest Mini2440-I Processor Card Features z z z z z z z z z Dimensions: 65mm x 45mm Temperature: 0~+70℃ Samsung's S3C2440A microcontroller based on a 1.33V Static ARM920T CPU core with MMU 64Mbyte SDRAM 32MB/128MB compatible 128Mbyte Nand flash (support 256Mbyte for option)

antifuse programming technology

Abstract: 40MX 42MX A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 42MX24
Contextual Info: v6.0 40MX and 42MX FPGA Families Fe a t ur es High C apaci t y • • • • • • Commercial, Military Temperature, and MIL-STD-883 Ceramic Packages Single-Chip ASIC Alternative 3,000 to 54,000 System Gates Up to 2.5 kbits Configurable Dual-Port SRAM

XC9572

Abstract: XC9572-10PC44C xc9572-15PQ100 15PC44I xc9572 data sheet XC9572-7PC44C PC44 PC84 xc9572-10pq100c XC9572-15PC84C
Contextual Info: XC9572 In-System Programmable CPLD R DS065 v4.2 April 15, 2005 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 72 macrocells with 1,600 usable gates Up to 72 user I/O pins 5V in-system programmable

XCR5128

Abstract: MC16 XCR3128 Xilinx XCR5128 P-QFP40
Contextual Info: APPLICATION NOTE This product has been discontinued. Please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. R DS041 v1.4 January 19, 2001 XCR5128: 128 Macrocell CPLD 14* Product Specification Features Description • The XCR5128 CPLD (Complex Programmable Logic

QL3012

Abstract: PF100 PF144 PL84 QL3012-1PF100C QL3012-1PQ144C
Contextual Info: QL3012 - pASIC 3 FPGATM 12,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density QL3012 - pASIC 3 FPGA DEVICE HIGHLIGHTS Device Highlights High Performance & High Density • 12,000 Usable PLD Gates with 118 I/Os ■ 16-bit counter speeds over 300 MHz, data path speeds over

MACH130-20

Abstract: MACH130 MACH230 PAL22V10 PAL26V16
Contextual Info: FINAL COM’L: -15/20 IND: -18/24 MACH130-15/20 Lattice Semiconductor High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 84 Pins 64 Outputs 64 Macrocells 64 Flip-flops; 4 clock choices 15 ns tPD Commercial 18 ns tPD Industrial 4 “PAL26V16” Blocks

CL-CD180

Abstract: Design a 3-bit magnitude comparator by using basic CL-CD1865 CL-CD1865-10QC-B diode D6E 80X86 CD1865 CL-CD1864 M68000 CD96
Contextual Info: CL-CD1865 Data Book FEATURES • Eight full-duplex asynchronous channels supporting data rates up to 115.2 kbps* Intelligent Eight-Channel Communications Controller ■ Register-based interrupt acknowledges eliminate need for separate interrupt acknowledge signals

94-by

Abstract: P101C TMP90CM38F
Contextual Info: TOSHIBA UNDER DEVELOPMENT CMOS 8-BIT TMP90CM38 M IC RO CO N T RO LLER T M P 9 0 C M 3 8 F /T M P9 0 C M 3 8T 1. OUTLINE A N D CHARACTERISTICS TMP90CM38 is a high speed, high performance 8-bit microcontroller developed for application in the control of various devices.

Contextual Info: Sipe* ’ C»p0f«»0n * SIGNAL PROCESSING EXCELLENCE PACKAGE: PLASTIC DUAL-IN-LINE NARROW m eA = 0.300 BSC (7.620 BSC) DIMENSIONS (Inches) M inim um /M axim um (mm) 160 8-PIN 14-PIN 16—PIN 18-PIN 20-PIN 22-PIN A2 0.115/0.195 (2.921/4.953) 0.115/0.195

Z80 KIO

Abstract: Z84C9008ASC Zilog Z80 KIO Z84C90 Z84C9008VEC Z84C9012VSC datasheet z80 Z84C90 KIO Z84C9008 Z84C30
Contextual Info: Z84C90 KIO Serial/Parallel Counter Timer Product Specification PS011802-0902 ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432 Telephone: 408.558.8500 • Fax: 408.558.8300 • http://www.ZiLOG.com This publication is subject to replacement by a later edition. To determine whether a later edition exists, or

Contextual Info: STP2021 S un M ic r o e l e c t r o n ic s J u ly 1997 PMC Power Management Controller DATA SHEET D e s c r ip t io n The STP2021 Power Management Controller brings power management to SBus-based systems. The STP2021 interfaces to the SBus via the byte-wide expansion bus EBus provided by the STP2001 Slave I/O Controller.