LH521002 Search Results

Contextual Info: LH521002A CMOS 256K x 4 Static RAM • Low Power Standby when Deselected High frequency design techniques should be em­ ployed to obtain the best performance from this device. Solid, low impedance power and ground planes, with high frequency decoupling capacitors, are desirable. Series

Contextual Info: LH521002C SHARP CMOS 256K x 4 Static RAM Data Sheet FEATURES The ‘L’ version will retain data down to a supply voltage of 2 V. A significantly lower current can be obtained Idr under this Data Retention condition. CMOS Standby Current (lSB2) ¡s reduced on the ‘L’ version with respect to

Contextual Info: SHARP CORP blE D • filflDTTfi OOO^flfi Mbb * S R P J LH521002 FEATURES • Fast Access Times: 20/25/35 ns • JEDEC Standard Pinouts • Low Power Standby when Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully Static Operation • Common I/O for Low Pin Count

LH521002AK25

Contextual Info: LH521002A CMOS 256K x 4 Static RAM • Low Power Standby when Deselected High frequency design techniques should be employed to obtain the best performance from this device. Solid, low impedance power and ground planes, with high frequency decoupling capacitors, are desirable. Series

S21002

Contextual Info: LH521002 FEATURES • Fast Access Times: 20 725/35 ns • High Density 28-Pin, 400-mil SOJ • JEDEC Standard Pinouts • Low Power Standby when Deselected • TTL Compatible I/O • 5 V± 10% Supply • Fully Static Operation • Common I/O for Low Pin Count

Contextual Info: SHARP LH521002C CMOS 256K x 4 Static RAM Data Sheet The ‘L’ version will retain data down to a supply voltage of 2 V. A significantly lower current can be obtained Idr under this Data Retention condition. CMOS Standby Current (lSB2) is reduced on the ‘L’ version with respect to

SOJ28-P-400

Contextual Info: LH521002C CMOS 256K x 4 Static RAM Data Sheet The ‘L’ version will retain data down to a supply voltage of 2 V. A significantly lower current can be obtained IDR under this Data Retention condition. CMOS Standby Current (ISB2) is reduced on the ‘L’ version with respect to

32-PIN

Contextual Info: LH521002B FEATURES • Fast Access Times: 17/20/25/35 ns • JEDEC Standard Pinouts • Low Power Standby when Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully Static Operation • 2 V Data Retention L Version • Packages: 28-pin, 300-mil SOJ (Preliminary)

km681001j-20

Abstract: TC55B328J-12 256Kx4 TC55B465J10 TC55B8128J20 PDM41028SA-15SO TC55B8128J-12 TC55328J-20 KM681001J-25 PDM41024S20
Contextual Info: Cross Reference Guide Cross Reference Guide ALLIANCE VS PARADIGM AS7C1024-10TJ AS7C1024-12TJ AS7C1024-15TJ AS7C1024-20TJ AS7C1024L-10TJ AS7C1024L-12TJ AS7C1024L-15TJ AS7C1024L-20TJ AS7C1028-10TJ AS7C1028-12TJ AS7C1028-15TJ AS7C1028-20TJ AS7C1028L-10TJ AS7C1028L-12TJ

lh57257

Abstract: IR2E31 IR2E01 IR2C07 IR2E27 IR2E24 IR2E19 IR2E31A IR3n06 IR2E02
Contextual Info: Index Model No. ARM7D CPU Core Bi-CMOS 1 27 40,42 _ _ CMOS CMOS CMOS CMOS CMOS 4A 5A 8 A AH D ID1 Series ID2 Series 40,42 40.42 40,42 40,42 40 B ü.’1*"! 14,15 14 m IR2339 IR2403 IR2406 IR2406G IR2410 IR2411 IR2415 IR2419 IR2420 IR2422 IR2425 IR2429

Contextual Info: MEMORIES * S tic RAMs Process C apacity Configuration Model No. A ccess tim e ns 70 80 90 100 120 LH5116 16k Full CMOS 64k 2k X 8 8k X 8 LH5116H f- Supply voltage : 5 V * 10% QpewBng tew ^raw » : ~ 40to85'C LH5116S j- Supply voltage : 3 V ± 10% LH5164A

BNK-17

Contextual Info: MEMORIES ★Under development • S ta tic RA M s Process Capacity Configuration words X bits Modal No. 2k X 8 Full CMOS 64k 8k X 8 256k 32k X 8 64k 8k X 8 64k X 4 256k 32k X 8 64k X 8 CMOS periphery 100 40/0.001 5 ± 10% O to 70 100 40/0.001 5 ± 10% - 4 0 to 85

Contextual Info: CMOS 256K x 4 Static RAM FEATURES • Fast Access Times: 20/25/35 ns • JEDEC Standard Pinouts Read cycles occur when E is LOW and W is HIGH. A Read cycle will^begin upon an addressjransition, on a falling edge of E, or on a rising edge of W. • 5 V ±10% Supply

LH5160N

Abstract: LH5115 LH5118D LH5160 LH5160D LH521000 LH5167 LH52252A LH5114H LH5911-55
Contextual Info: NOV 0 5 1990 L H 5 9 1 1 /L H 5 9 1 2 /L H 5 9 1 4 2K x 8 CMOS Dual Port RAM Preliminary Data Sheet Features Functional Description The IH 5911, LH5912 and LH5914are dual port static RAMs that use true dual port memory cells to allow each port to independently access any location in memory.

organizational structure samsung

Abstract: NMS256X8 MICRON Cross Reference NMS256 256K RAM HM62256 MK6264 51256SL TC5565 "cross reference" MN44256 M5M5256
Contextual Info: Static RAM Cross Reference STATIC RAM CROSS REFERENCE ORGANIZATIONAL STRUCTURE 2K 2K X X 32K 8K X e w/CE, OE 8 W/CE1, CE2 X 8 Stow 8 Slow COMPETITIVE VENDOR SH ARP MODEL LH5116 LH5118 LH51256 LH5164A AMD Am9128 Harris CDM6116 Hitachi HM6116A Hyundai HY6116

521002

Abstract: lh521002
Contextual Info: C M O S 256K x 4 Static RAM FEATURES • Fast Access Times: 20/25/35 ns • Low Power Standby when Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully Static Operation • Common I/O for Low Pin Count • 2 V Data Retention • JEDEC Standard Pinouts

LH5911

Abstract: lh5167-55 LH5101 LH52250 LH5160D LH5167 LH52252 LH5114H lh5160n 4kx8 static ram ttl
Contextual Info: NOV 0 5 1990 L H 5 9 1 1 /L H 5 9 1 2 /L H 5 9 1 4 2K x 8 CMOS Dual Port RAM Preliminary Data Sheet Functional Description Features The LH5911. LH5912 and LH5914are dual port static RAMs that use true dual port memory cells to allow each port to independently access any location in memory.

lh5168

Contextual Info: MEMORIES Static RAMs ★ Under development P ro ce ss C a p a c ity C o n fig u ra tio n Model No. A c c e s s tim e n s 70 80 90 100 120 LH5116 2k X 8 16k LH51116H Operating temperature : - 40 to 8 5 t IUUU "O LH5116S Supply voltage : 3 V±10% LH5168 Full

5268A

Abstract: 28-SOP LH521002AK-2S 28SOP LH52256CVN
Contextual Info: MEMORIES S tatic RAMs Process Capacity Configuation words Xbits 2k 16k 8 X Access time Supply current ns) MAX. Cycle time Operating, Standby (ns) MIN. !mA) MAX. (mA) MAX. Model No. Supply Operating voltage temp. 0C) m i i LH 5116/NA/D-10 100 40 0.001 5 ± 10%

Spil polyimide system in package

Abstract: B-629
Contextual Info: SHARP LH521007C Data Sheet CMOS 128K X 8 Static RAM FEATURES When both Chip Enables are active and W is inactive, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation,

9660t

Abstract: LH521008
Contextual Info: SHARP b OE CORP D • Ô1ÔD7TÔ DDDTME? 302 «SRPJ 'T - H C - 2 3 - / O LH101504 LH101510 . R E L I M I N A Ü 3 H 1 3 C5 WF A,s Au Ai 3 R Y High-Speed BiCMOS 1M 1M xi ECL Static RAM ■ Description ■ The LH101504/LH101510 is a 256K/1M-bit high speed

LH521007AK-20

Contextual Info: STATIC RAM ☆ New product ★ Under development STATIC RAMs ♦ Features • The product lineup includes a wide variety of bit configurations x4, x8, x l6 , x l8 , x32 . • High-speed synchronous devices for the secondary cache memory are available for use with low-voltage, lowpower CPUs idpal for portable equipment.

MB821

Abstract: LH521002K-20 KM641001-20 UPD431004LE-25 UPD431004LE-20 KM641001-25 KM641001-35 LH521002K-25 t5c1 t5c1005
Contextual Info: - 145 m s it £ ÎS Â ÏE H OC RAM 2 6 2 1 4 4 x 4 ) IM CMOS S t a t i c X 'i 7 f y 7 # t ì TAAC sax (ns) TCAC •ax (ns) TOE max TOH nin (ns) (ns) TOD nax (ns) TWP tin (ns) % TDS rain TDH TWD min (ni;) (ns) (ns) TWR œax (ns) VC'D or V C C (V) 28 PI N

LHS168

Abstract: LH52252A LH52252
Contextual Info: V .J 1 íVt! Static RAMs ★Under development Process Capacity Model No. Configuration Access time ns 70 -I 16k 2k Package 90 100 120 LH5116 J— I. 24 24 24 LH5116H 3 -T 24 24 24 - Z ÏÏ-J 1 24 24 24 C E , C S c o n tro l Data retention current : 0.2 pAjMAXj j