LH521007 Search Results

LH521007AK-25

Abstract: lh521007ak 32-PIN
Contextual Info: LH521007A FEATURES • Fast Access Times: 17/20/25 ns • Two Chip Enable Controls • Low-Power Standby When Deselected • TTL Compatible I/O • 5 V ±10% Supply • Fully-Static Operation • 2 V Data Retention • Package: 32-Pin, 400-mil SOJ FUNCTIONAL DESCRIPTION

32-PIN

Contextual Info: LH521007B FEATURES • Fast Access Times: 17/20/25/35 ns • Two Chip Enable Controls • Low Power Standby When Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully Static Operation • 2 V Data Retention L Version • Packages: 32-Pin, 300-mil SOJ (Preliminary)

Spil polyimide system in package

Abstract: B-629
Contextual Info: SHARP LH521007C Data Sheet CMOS 128K X 8 Static RAM FEATURES When both Chip Enables are active and W is inactive, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation,

lh521007

Contextual Info: PRELIMINARY LH521007/ FEATURES • Fast Access Times: 20 725/35 ns • Two Chip Enable Controls • High Density 32-Pin, 400-mil SOJ • Low Power Standby When Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully Static Operation • 2 V Data Retention

DIP32-P-400

Contextual Info: PRELIMINARY LH521007 FEATURES • Fast Access Times: 20/25/35 ns • Two Chip Enable Controls • Low Power Standby When Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully Static Operation • 2 V Data Retention • Packages: 32-Pin, 400-mil DIP

Contextual Info: SHARP LH521007C CMOS 128K x 8 Static RAM Data Sheet When both Chip Enables are active and W is inactive, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation,

32-PIN

Abstract: SOJ32-P-300
Contextual Info: LH521007C CMOS 128K x 8 Static RAM Data Sheet When both Chip Enables are active and W is inactive, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation,

SOJ32

Abstract: 32-PIN SOJ32-P-300 LH521007ck
Contextual Info: LH521007C CMOS 128K x 8 Static RAM Data Sheet When both Chip Enables are active and W is inactive, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation,

lh57257

Abstract: IR2E31 IR2E01 IR2C07 IR2E27 IR2E24 IR2E19 IR2E31A IR3n06 IR2E02
Contextual Info: Index Model No. ARM7D CPU Core Bi-CMOS 1 27 40,42 _ _ CMOS CMOS CMOS CMOS CMOS 4A 5A 8 A AH D ID1 Series ID2 Series 40,42 40.42 40,42 40,42 40 B ü.’1*"! 14,15 14 m IR2339 IR2403 IR2406 IR2406G IR2410 IR2411 IR2415 IR2419 IR2420 IR2422 IR2425 IR2429

Contextual Info: MEMORIES * S tic RAMs Process C apacity Configuration Model No. A ccess tim e ns 70 80 90 100 120 LH5116 16k Full CMOS 64k 2k X 8 8k X 8 LH5116H f- Supply voltage : 5 V * 10% QpewBng tew ^raw » : ~ 40to85'C LH5116S j- Supply voltage : 3 V ± 10% LH5164A

BNK-17

Contextual Info: MEMORIES ★Under development • S ta tic RA M s Process Capacity Configuration words X bits Modal No. 2k X 8 Full CMOS 64k 8k X 8 256k 32k X 8 64k 8k X 8 64k X 4 256k 32k X 8 64k X 8 CMOS periphery 100 40/0.001 5 ± 10% O to 70 100 40/0.001 5 ± 10% - 4 0 to 85

Contextual Info: CMOS 128K x 8 S tatic RAM FEATURES • Fast Access Times: 17/20/25 ns • Two Chip Enable Controls • Low-Power Standby When Deselected • TTL Compatible I/O • 5 V ±10% Supply • Fully-Static Operation • 2 V Data Retention • Package: 32-Pin, 400-mil SOJ

LQ070T5BG01

Abstract: LM24P20 LM162KS1 BSCR86L00 IR2C07 LM5Q31 IR3Y29B BSCU86L60 lq6bw lq6bw506
Contextual Info: INDEX 1 0 4 - 1 0 9 _ DC_ GL1PR112.69 GL3KG63. 66 GL5EG41.66 1 0 4 - n 0 5 O o c .113 DC1B1CP. 100 GL1PR135.69 GL3KG8. 66

organizational structure samsung

Abstract: NMS256X8 MICRON Cross Reference NMS256 256K RAM HM62256 MK6264 51256SL TC5565 "cross reference" MN44256 M5M5256
Contextual Info: Static RAM Cross Reference STATIC RAM CROSS REFERENCE ORGANIZATIONAL STRUCTURE 2K 2K X X 32K 8K X e w/CE, OE 8 W/CE1, CE2 X 8 Stow 8 Slow COMPETITIVE VENDOR SH ARP MODEL LH5116 LH5118 LH51256 LH5164A AMD Am9128 Harris CDM6116 Hitachi HM6116A Hyundai HY6116

mn4117405

Abstract: NN5118165 XL93LC46AP NN514265 MS6264L-10PC w24M257 NN514265A w24m257ak-15 HY62256ALP10 mhs p80c51
Contextual Info: ISSI CROSS REFERENCE GUIDE Integrated Silicon Solution, Inc. ISSI ® Integrated Silicon Solution, Inc. CROSS REFERENCE GUIDE SRAM DRAM EEPROM EPROM MICROCONTROLLER JUNE 1999 Integrated Silicon Solution, Inc. CP005-1F 6/1/99 1 ISSI CROSS REFERENCE GUIDE

UM61256AK-15

Abstract: UM61256ak sram um61256ck-20 HY62256ALP10 XL93LC46AP w24m257 GVT7164D32Q-6 km62256blg-7 w24m257ak-15 UM61256
Contextual Info: ISSI CROSS REFERENCE GUIDE Integrated Silicon Solution, Inc. ISSI ® Integrated Silicon Solution, Inc. CROSS REFERENCE GUIDE SRAM DRAM EEPROM EPROM FLASH MICROCONTROLLER SERIAL FLASH JULY 1998 Integrated Silicon Solution, Inc. CP005-1E 7/1/98 1 ISSI CROSS REFERENCE GUIDE

lh5168

Contextual Info: MEMORIES Static RAMs ★ Under development P ro ce ss C a p a c ity C o n fig u ra tio n Model No. A c c e s s tim e n s 70 80 90 100 120 LH5116 2k X 8 16k LH51116H Operating temperature : - 40 to 8 5 t IUUU "O LH5116S Supply voltage : 3 V±10% LH5168 Full

Contextual Info: CMOS 128K x 8 Static RAM FEATURES • Fast Access Times: 20/25/35 ns • Two Chip Enable Controls • Low-Power Standby When Deselected • TTL Compatible I/O • 5 V ±10% Supply • Fully-Static Operation • 2 V Data Retention • Package: 32-Pin, 400-mil SOJ

5268A

Abstract: 28-SOP LH521002AK-2S 28SOP LH52256CVN
Contextual Info: MEMORIES S tatic RAMs Process Capacity Configuation words Xbits 2k 16k 8 X Access time Supply current ns) MAX. Cycle time Operating, Standby (ns) MIN. !mA) MAX. (mA) MAX. Model No. Supply Operating voltage temp. 0C) m i i LH 5116/NA/D-10 100 40 0.001 5 ± 10%

LH521007AK-20

Contextual Info: STATIC RAM ☆ New product ★ Under development STATIC RAMs ♦ Features • The product lineup includes a wide variety of bit configurations x4, x8, x l6 , x l8 , x32 . • High-speed synchronous devices for the secondary cache memory are available for use with low-voltage, lowpower CPUs idpal for portable equipment.

um61256ak-15

Abstract: w24m257ak-15 um61256 um61256ck-20 um61256ak-12 km62256blg-7 KM68257Bp-20 W24M257AK HY6264ALP-10 w24M257
Contextual Info: ISSI Integrated Silicon Solution, Inc. CROSS REFERENCE GUIDE SRAM/NVM Serial EEPROM EPROM FLASH Static RAM SEPTEMBER 1996 CROSS REFERENCE GUIDE E2PROM ATMEL ISSI MIL PACKAGE SYMBOL PC P SC G SC GR AT93C46-10PC AT93C46-10PC-2.7 AT93C46-10SC AT93C46-10SC-2.7

LHS168

Abstract: LH52252A LH52252
Contextual Info: V .J 1 íVt! Static RAMs ★Under development Process Capacity Model No. Configuration Access time ns 70 -I 16k 2k Package 90 100 120 LH5116 J— I. 24 24 24 LH5116H 3 -T 24 24 24 - Z ÏÏ-J 1 24 24 24 C E , C S c o n tro l Data retention current : 0.2 pAjMAXj j

IR2E27A

Abstract: IR2C53 IR2E02 IR2E27 IR2E10 IR3N34 IR2E31A IR2E01 IR2C07 ir2e31
Contextual Info: lndeX Model No. ARM7D CPU Core28,32,33 ARM7DM 28,33 CMOS CMOS CMOS CMOS 76 5A A F G 44 44 44 44 ID1 series ID2 series ID3 seríes ID21K064 ID21K128 ID21K256 ID21K512 ID21M010 ID21M015 ID21M020 ID21M040 ID22K256 ID22K512 ID22M010 ID22M020 ID22M040 ID22M080

Contextual Info: CMOS 128K x 8 Static RAM FEATURES • Fast Access Times: 17/20/25/35 ns • Two Chip Enable Controls • Low Power Standby When Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully Static Operation • 2 V Data Retention L Version • Packages: