TP0606 Search Results

Contextual Info: TP0606 P-Channel Enhancement-Mode Vertical DMOS FET Features General Description ► ► ► ► ► ► ► ► This low threshold, enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This

Contextual Info: TP0606 Supertex inc. Low Threshold P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information b v dss/ R d S ON I d (ON) ^GS(th) Order Num ber / Package b v dgs (max) (min) (max) TO-92 -60V 3.5Î2 -1.5A -2.4V TP0606N3 Features □ Low threshold — 2.4V max

FAST DMOS FET Switches

Abstract: TP0606N7 TP0606N6 DMOS FET P-Channel Enhancement Mode Vertical DMOS FET FAST DMOS FET Switches p-CHANNEL mos die MOS FET Array p-channel DMOS Photo MOS Relay
Contextual Info: TP0606N6 TP0606N7 Low Threshold P-Channel Enhancement-Mode Vertical DMOS FET Quad Array Ordering Information BVDSS / BVDGS RDS ON (max) -60V 3.5Ω Order Number / Package 14-Pin P-Dip 14-Pin C-Dip* TP0606N6 TP0606N7 * 14 pin side brazed ceramic DIP Advanced DMOS Technology

Contextual Info: TP0606N6 Transistors P-Channel Enhancement Mode MOSFET Array Military/High-RelN V BR DSS (V)60 V(BR)GSS (V) I(D) Max. (A)650m I(DM) Max. (A) Pulsed I(D) @Temp (øC) IDM Max (@25øC Amb)3.5 @Pulse Width (s) (Condition)300u Absolute Max. Power Diss. (W)3.0 Minimum Operating Temp (øC)-55

Contextual Info: TP0606N2 Transistors P-Channel Enhancement MOSFET Military/High-RelN V BR DSS (V)60 V(BR)GSS (V)20 I(D) Max. (A)1.0 I(DM) Max. (A) Pulsed I(D) @Temp (øC) IDM Max (@25øC Amb)4.0 @Pulse Width (s) (Condition)300u Absolute Max. Power Diss. (W)6.0 Minimum Operating Temp (øC)-55

TP0606N5

Contextual Info: TP0606 TP0610 S u p e r t e x in c . Low Threshold P-Channel Enhancement-Mode Vertical DMOS FETs If Ordering Information Order Num ber / Package B W B V jx -s ^DS ON ^GS(lh) (max) (max) TO-39 TO-92 TO-220 -60V 3 .5 ft -1.5A -2.4V — TP0606N3 TP0606N5 -100V

TP0606N3-G

Contextual Info: Supertex inc. TP0606 P-Channel Enhancement-Mode Vertical DMOS FET Features General Description Low threshold -2.4V max. High input impedance Low input capacitance (80pF typ.) Fast switching speeds Low on-resistance Free from secondary breakdown Low input and output leakage

TP0606

Contextual Info: TP0606 P-Channel Enhancement-Mode Vertical DMOS FET Features General Description ► ► ► ► ► ► ► ► This low threshold, enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This

TP0606N5

Abstract: TP0610N3 TP0610N2 TP0606 TP0606N2 TP0606N3 TP0606N6 TP0610 TP0610N5 Tp0606N7
Contextual Info: TP0606 TP0610 Low Threshold P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information BVDSS / RDS ON BVDGS (max) Order Number / Package ID(ON) (min) VGS(th) (max) TO-39 TO-92 TO-220 Quad P-DIP Quad C-DIP* DICE† -60V 3.5Ω -1.5A -2.4V TP0606N2

SITP

Abstract: Tp0606 TP0606N3-G
Contextual Info: TP0606 P-Channel Enhancement-Mode Vertical DMOS FET Features General Description ► ► ► ► ► ► ► This low threshold, enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This

TP0606

Abstract: TP0606N3
Contextual Info: TP0606 Low Threshold P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information BVDSS / BVDGS RDS ON (max) ID(ON) (min) VGS(th) (max) Order Number / Package -60V 3.5Ω -1.5A -2.4V TP0606N3 TO-92 Features Low Threshold DMOS Technology ❏ Low threshold — -2.4V max

TP0606N7

Contextual Info: TP0606N6 TP0606N7 Çh Super te x inc. Low Threshold P-Channel Enhancement-Mode Vertical DMOS FET Quad Array Ordering Information BVdss / BVdgs RdS ON (max) -60V 3.5£2 Order Number / Package 14-Pin P-Dip 14-Pin C-Dip* TP0606N6 TP0606N7 14 pin side brazed ceramic DIP

TP0606

Abstract: TP0606N3
Contextual Info: TP0606 Low Threshold P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information BVDSS / RDS ON BVDGS (max) -60V 3.5Ω ID(ON) (min) VGS(th) (max) Order Number / Package -1.5A -2.4V TP0606N3 TO-92 7 Features Low Threshold DMOS Technology • Low threshold — -2.4V max

Tp0606N7

Contextual Info: TP0606N7 Transistors P-Channel Enhancement Mode MOSFET Array Military/High-RelN V BR DSS (V)60 V(BR)GSS (V)20 I(D) Max. (A)750m I(DM) Max. (A) Pulsed I(D) @Temp (øC) IDM Max (@25øC Amb)3.5 @Pulse Width (s) (Condition)300u Absolute Max. Power Diss. (W)4.0

TP060

Abstract: TP0606N7
Contextual Info: TP0606N6 TP0606N7 Low Threshold P-Channel Enhancement-Mode Vertical DMOS FET Quad Array Ordering Information b v dss/ ^DS ON b v dgs (max) -60V 3.5Q Order Number / Package 14-Pin P-Dip 14-Pin C-Dip* TP0606N6 TP0606N7 * 14 pin side brazed ceram ic DIP Advanced DMOS Technology

TP0606

Contextual Info: TP0606 Die Specification Pad Layout 1 0,0 2 Backside: Drain Die Specifications Die Dimensions Device Length Width Thickness mils Back Side Metal 45 45 11 ± 1.5 Au 1 (mils) TP0606 1 (mils) Back Side Bonding Pad Material Bond Wire Bond Wire Size Drain Al/Cu/Si

TP0610N3

Abstract: TP0606N5 TP0606 TP0606N3 TP0610 TP0610N2
Contextual Info: TP0606 TP0610 Low Threshold P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information BVDSS / RDS ON BVDGS (max) Order Number / Package ID(ON) (min) VGS(th) (max) TO-39 TO-92 TO-220 -60V 3.5Ω -1.5A -2.4V — TP0606N3 TP0606N5 -100V 3.5Ω -1.5A

TP0606N5

Contextual Info: TP0606N5 Transistors P-Channel Enhancement MOSFET Military/High-RelN V BR DSS (V)60 V(BR)GSS (V)20 I(D) Max. (A)2.0 I(DM) Max. (A) Pulsed I(D) @Temp (øC) IDM Max (@25øC Amb)4.5 @Pulse Width (s) (Condition)300u Absolute Max. Power Diss. (W)45 Minimum Operating Temp (øC)-55

Contextual Info: TP0606 TP0610 Law Threshold mm\ g « « « P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information Order Number / Package b v dss/ ^D S O N ^D(ON) ^G S (th ) b v dgs (max) (min) (max) TO-39 TO-92 TO-220 Quad P-DIP Quad C-DIP* -60V 3.5Q -1.5A -2.4V

TP0606N6

Contextual Info: ^ S u p ertex tnc. TP0606N6 TP0606N7 Low Threshold P-Channel Enhancement-Mode Vertical DMOS FET Quad Array Ordering Information Standard Commercial Devices BVDSS/ R d s <ON BVoos max) -60V 3.5 a Order Number / Package 14-Pin C-Dip* 14-Pin P-Dip TP0606N7

TP0606N5

Abstract: TP0610 TP0606N3 TP0610N2 TP0610N5
Contextual Info: TP0606 TP0610 Supertex inc. M Low Threshold P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information Order Number / Package BVDSS/ ^DS ON ' d (ON) ^GSfth) Bv dgs (max) (min) (max) TO-39 TO-92 TO-220 Quad P-DIP Quad C-DIP* -60V 3.5Π-1.5A -2.4V

Contextual Info: TP0606N3 Transistors P-Channel Enhancement MOSFET Military/High-RelN V BR DSS (V)60 V(BR)GSS (V)20 I(D) Max. (A)500m I(DM) Max. (A) Pulsed I(D) @Temp (øC) IDM Max (@25øC Amb)3.5 @Pulse Width (s) (Condition)300u Absolute Max. Power Diss. (W)1.0 Minimum Operating Temp (øC)-55

TP0606

Contextual Info: Supertex inc. TP0606 Die Specification Pad Layout 1 0,0 2 Backside: Drain Die Specifications Die Dimensions Device Length Width Thickness mils Back Side Metal 45 45 11 ± 1.5 Au 1 (mils) TP0606 1 (mils) Back Side Bonding Pad Material Drain Al/Cu/Si Bonding Pad Description

TP06A

Contextual Info: TP06A ^ Supertex inc- Low Threshold P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information Standard Commercial Devices BV qgs ^DSfON If BVDSS/ max) V Order Number / Package g s (Ui ) (max) -60 V 3 .5 n -1.5A -2.4V -100V 3.5Î2 -1.5A -2.4V TO-39