APPLICATION NOTE TSSOP5 NXP Search Results

Contextual Info: 74LVC1G04 Single inverter Rev. 9 — 26 October 2010 Product data sheet 1. General description The 74LVC1G04 provides one inverting buffer. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.

74AHC1G09-Q100

Contextual Info: 74AHC1G09-Q100 2-input AND gate with open-drain output Rev. 2 — 16 August 2012 Product data sheet 1. General description The 74AHC1G09-Q100 is a high-speed Si-gate CMOS device. The 74AHC1G09-Q100 provides the 2-input AND function with open-drain output.

v08 smd marking code

Abstract: NXP date code marking nxp Standard Marking SOT1202 SOT1115 marking nxp package 74LVC1G08GW
Contextual Info: 74LVC1G08 Single 2-input AND gate Rev. 8 — 19 October 2010 Product Specification 1. General description The 74LVC1G08 provides one 2-input AND function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.

JESD22-A114E

Abstract: MO-203 XC7SET14 XC7SET14GW
Contextual Info: XC7SET14 Inverting Schmitt trigger Rev. 01 — 31 August 2009 Product data sheet 1. General description XC7SET14 is a high-speed Si-gate CMOS device. It provides an inverting buffer function with Schmitt trigger action. This device is capable of transforming slowly changing input

Contextual Info: XC7SET14 Inverting Schmitt trigger Rev. 01 — 31 August 2009 Product data sheet 1. General description XC7SET14 is a high-speed Si-gate CMOS device. It provides an inverting buffer function with Schmitt trigger action. This device is capable of transforming slowly changing input

74AUP1G132GF

Abstract: 74AUP1G132GM 74AUP1G132GW JESD22-A114E MO-203
Contextual Info: 74AUP1G132 Low-power 2-input NAND Schmitt trigger Rev. 02 — 15 June 2009 Product data sheet 1. General description The 74AUP1G132 provides the single 2-input NAND Schmitt trigger function which accept standard input signals. They are capable of transforming slowly changing input signals

74AHC1G09-Q100

Contextual Info: 74AHC1G09-Q100 2-input AND gate with open-drain output Rev. 2 — 16 August 2012 Product data sheet 1. General description The 74AHC1G09-Q100 is a high-speed Si-gate CMOS device. The 74AHC1G09-Q100 provides the 2-input AND function with open-drain output.

74LVC1G04GW

Abstract: JESD87
Contextual Info: 74LVC1G04 Single inverter Rev. 08 — 27 April 2009 Product data sheet 1. General description The 74LVC1G04 provides one inverting buffer. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.

JESD22-A114E

Abstract: MO-203
Contextual Info: XC7SH14 Inverting Schmitt trigger Rev. 01 — 1 September 2009 Product data sheet 1. General description XC7SH14 is a high-speed Si-gate CMOS device. It provides an inverting buffer function with Schmitt trigger action. This device is capable of transforming slowly changing input

Contextual Info: 74LVC1GU04 Inverter Rev. 11 — 2 July 2012 Product data sheet 1. General description The 74LVC1GU04 provides the inverting single state unbuffered function. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

Contextual Info: XC7SH14 Inverting Schmitt trigger Rev. 01 — 1 September 2009 Product data sheet 1. General description XC7SH14 is a high-speed Si-gate CMOS device. It provides an inverting buffer function with Schmitt trigger action. This device is capable of transforming slowly changing input

Contextual Info: 74AHC1G32-Q100; 74AHCT1G32-Q100 2-input OR gate Rev. 1 — 11 July 2012 Product data sheet 1. General description 74AHC1G32-Q100 and 74AHCT1G32-Q100 are high-speed Si-gate CMOS devices. They provide a 2-input OR function. The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V.

application note tssop5 nxp

Contextual Info: 74LVC1G06 Inverter with open-drain output Rev. 10 — 29 June 2012 Product data sheet 1. General description The 74LVC1G06 provides the inverting buffer. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.

Contextual Info: 74LVC1G07 Buffer with open-drain output Rev. 11 — 29 June 2012 Product data sheet 1. General description The 74LVC1G07 provides the non-inverting buffer. The output of this device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.

Contextual Info: 74AUP1GU04 Low-power unbuffered inverter Rev. 4 — 16 November 2011 Product data sheet 1. General description The 74AUP1GU04 provides the single unbuffered inverting gate. This device ensures a very low static and dynamic power consumption across the entire

Contextual Info: 74LVC1G38 2-input NAND gate; open drain Rev. 7 — 4 October 2012 Product data sheet 1. General description The 74LVC1G38 provides a 2-input NAND function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device as translator in a mixed 3.3 V and 5 V environment.

Contextual Info: 74LVC1GU04 Inverter Rev. 11 — 2 July 2012 Product data sheet 1. General description The 74LVC1GU04 provides the inverting single state unbuffered function. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

74AHC1G14

Abstract: 74AHC1G14GV 74AHC1G14GW 74AHCT1G14 74AHCT1G14GV 74AHCT1G14GW JESD22-A114E marking af sot353
Contextual Info: 74AHC1G14; 74AHCT1G14 Inverting Schmitt trigger Rev. 05 — 29 June 2007 Product data sheet 1. General description 74AHC1G14 and 74AHCT1G14 are high-speed Si-gate CMOS devices. They provide an inverting buffer function with Schmitt trigger action. These devices are capable of

74AUP1G132GF

Abstract: 74AUP1G132GM 74AUP1G132GW MO-203
Contextual Info: 74AUP1G132 Low-power 2-input NAND Schmitt trigger Rev. 01 — 20 October 2006 Product data sheet 1. General description The 74AUP1G132 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

JESD22-A114E

Contextual Info: 74AUP1G09 Low-power 2-input AND gate with open-drain Rev. 2 — 9 July 2010 Product data sheet 1. General description The 74AUP1G09 provides the single 2-input AND gate with an open-drain output. The output of the device is an open-drain and can be connected to other open-drain outputs to

Contextual Info: 74LVC1GU04 Unbuffered inverter Rev. 12 — 9 April 2013 Product data sheet 1. General description The 74LVC1GU04 is a single unbuffered inverter. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

6E-15

Contextual Info: 74LVC1G08 Single 2-input AND gate Rev. 10 — 29 June 2012 Product data sheet 1. General description The 74LVC1G08 provides one 2-input AND function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.

Contextual Info: 74LVC1G02 Single 2-input NOR gate Rev. 11 — 29 June 2012 Product data sheet 1. General description The 74LVC1G02 provides the single 2-input NOR function. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.

Contextual Info: 74AHC1GU04-Q100 Inverter Rev. 1 — 21 November 2012 Product data sheet 1. General description The 74AHC1GU04-Q100 is a high-speed Si-gate CMOS device. It provides an inverting single stage function. The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V.