CD4042B Search Results

CD4042

Abstract: CD4042B MTSS001C SCHS040D pw mo-153
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS040D − Revised October 2003 The CD4042B types are supplied in 16-lead hermetic dual-in-line ceramic packages F3A suffixes , 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (D, DR, DT, DW, DWR, and NSR

CD4042BMS

Abstract: IOH15
Contextual Info: CD4042BMS S E M I C O N D U C T O R CMOS Quad Clocked “D” Latch December 1992 Features Pinout • High-Voltage Type 20V Rating CD4042BMS TOP VIEW • Clock Polarity Control • Q and Q Outputs Q4 1 16 VDD • Common Clock Q1 2 15 Q4 • Low Power TTL Compatible

d4042

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS040D − Revised October 2003 The CD4042B types are supplied in 16-lead hermetic dual-in-line ceramic packages F3A suffixes , 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (D, DR, DT, DW, DWR, and NSR

CD4042B

Abstract: CD4042BD CD4042BDE4 CD4042BDR CD4042BDRE4 CD4042BDT CD4042BDTE4 CD4042BDW CD4042BDWE4 CD4042BDWR
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS040D − Revised October 2003 The CD4042B types are supplied in 16-lead hermetic dual-in-line ceramic packages F3A suffixes , 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (D, DR, DT, DW, DWR, and NSR

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS040D − Revised October 2003 The CD4042B types are supplied in 16-lead hermetic dual-in-line ceramic packages F3A suffixes , 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (D, DR, DT, DW, DWR, and NSR

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS040D − Revised October 2003 The CD4042B types are supplied in 16-lead hermetic dual-in-line ceramic packages F3A suffixes , 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (D, DR, DT, DW, DWR, and NSR

CD4042BMS

Abstract: IOH15
Contextual Info: CD4042BMS CMOS Quad Clocked “D” Latch December 1992 Features Pinout • High-Voltage Type 20V Rating CD4042BMS TOP VIEW • Clock Polarity Control • Q and Q Outputs Q4 1 16 VDD • Common Clock Q1 2 15 Q4 • Low Power TTL Compatible Q1 3 14 D4 D1 4

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS040D − Revised October 2003 The CD4042B types are supplied in 16-lead hermetic dual-in-line ceramic packages F3A suffixes , 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (D, DR, DT, DW, DWR, and NSR

IC CD4042B

Contextual Info: CD4042B Types ^O ^ TŸ CMOS Quad Clocked "D” Latch High-Voltage Types 20-Volt Rating) The RCA-CD4042B types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are availa­ ble from each circuit. The impedance of the

4042B

Contextual Info: CD4042BM/CD4042BC National Semiconductor CD4042BM/CD4042BC Quad Clocked D Latch General Description Features The CD4042BM/CD4042BC quad clocked “ D” latch is a monolithic complementary MOS CMOS integrated circuit constructed with P- and N-channel enhancement mode

CD4042B

Abstract: CD4042BD CD4042BDE4 CD4042BDG4 CD4042BDR CD4042BDRE4 CD4042BDRG4 CD4042BDT CD4042BDTE4 CD4042BDTG4
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS040D − Revised October 2003 The CD4042B types are supplied in 16-lead hermetic dual-in-line ceramic packages F3A suffixes , 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (D, DR, DT, DW, DWR, and NSR

CD4042B

Abstract: MS-001 MSOI003E
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS040C – Revised February 2003 The CD4042B types are supplied in 16-lead hermetic dual-in-line ceramic packages F3A suffixes , 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (D, DR, DW, DWR, and NSR suffixes),

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS040C – Revised February 2003 The CD4042B types are supplied in 16-lead hermetic dual-in-line ceramic packages F3A suffixes , 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (D, DR, DW, DWR, and NSR suffixes),

74LS

Abstract: CD4042B CD4042BC CD4042BM
Contextual Info: CD4042BM/CD4042BC National JSmSemiconductor CD4042BM/CD4042BC Quad Clocked D Latch General Description Features The CD4042BM/CD4042BC quad clocked “ D” latch is a monolithic complementary MOS CMOS integrated circuit constructed with P- and N-channel enhancement mode

CD4042B

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS040A – Revised March 2002 The CD4042B types are supplied in 16-lead hermetic dual-in-line ceramic packages D and F suffixes , 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline package (NSR suffix), and in chip form (H

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS040D − Revised October 2003 The CD4042B types are supplied in 16-lead hermetic dual-in-line ceramic packages F3A suffixes , 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (D, DR, DT, DW, DWR, and NSR

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS040D − Revised October 2003 The CD4042B types are supplied in 16-lead hermetic dual-in-line ceramic packages F3A suffixes , 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (D, DR, DT, DW, DWR, and NSR

CD4042BMS

Abstract: IOH15
Contextual Info: CD4042BMS CMOS Quad Clocked “D” Latch December 1992 Features Pinout • High-Voltage Type 20V Rating CD4042BMS TOP VIEW • Clock Polarity Control • Q and Q Outputs Q4 1 16 VDD • Common Clock Q1 2 15 Q4 • Low Power TTL Compatible Q1 3 14 D4 D1 4

CD4042B

Abstract: CD4042BD CD4042BDE4 CD4042BDG4 CD4042BDR CD4042BDRE4 CD4042BDRG4 CD4042BDT CD4042BDTE4 CD4042BDTG4
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS040D − Revised October 2003 The CD4042B types are supplied in 16-lead hermetic dual-in-line ceramic packages F3A suffixes , 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (D, DR, DT, DW, DWR, and NSR

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS040D − Revised October 2003 The CD4042B types are supplied in 16-lead hermetic dual-in-line ceramic packages F3A suffixes , 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (D, DR, DT, DW, DWR, and NSR

cd4042bcn

Abstract: 74LS C1995 CD4042B CD4042BC CD4042BCJ CD4042BM CD4042BMJ J16A
Contextual Info: CD4042BM CD4042BC Quad Clocked D Latch General Description Features The CD4042BM CD4042BC quad clocked ‘‘D’’ latch is a monolithic complementary MOS CMOS integrated circuit constructed with P- and N-channel enhancement mode transistors The outputs Q and Q either latch or follow the

CD4042B

Abstract: CD4042BD CD4042BDE4 CD4042BDR CD4042BDRE4 CD4042BDT CD4042BDTE4 CD4042BDW CD4042BDWE4 CD4042BDWR
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS040D − Revised October 2003 The CD4042B types are supplied in 16-lead hermetic dual-in-line ceramic packages F3A suffixes , 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (D, DR, DT, DW, DWR, and NSR

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS040D − Revised October 2003 The CD4042B types are supplied in 16-lead hermetic dual-in-line ceramic packages F3A suffixes , 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (D, DR, DT, DW, DWR, and NSR

CD4042BMJ

Contextual Info: CD4G42BM/CD4042BC ¡^National Semiconductor CD4042BM/CD4042BC Quad Clocked D Latch ‘-Ct General Description Features The CD4Q42BM/CD4042BC quad clocked “ O” latch is a monolithic complementary MOS CMOS integrated cir­ cuit constructed with P- and N-channel enhancement