CD74HCT10 Search Results

CD74HCT10 Result Highlights (5)

Part	Manufacturer	Description
CD74HCT10M96G4	Texas Instruments	High Speed CMOS Logic Triple 3-Input NAND Gates 14-SOIC -55 to 125
CD74HCT109M	Texas Instruments	High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125
CD74HCT10M	Texas Instruments	High Speed CMOS Logic Triple 3-Input NAND Gates 14-SOIC -55 to 125
CD74HCT10M96	Texas Instruments	High Speed CMOS Logic Triple 3-Input NAND Gates 14-SOIC -55 to 125
CD74HCT109E	Texas Instruments	High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125

CD74HCT10 Price and Stock

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Rochester Electronics LLC CD74HCT10E IC GATE NAND 3CH 3-INP 14DIP
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CD74HCT10E	Bulk	32,575		888	1 - 10 - 100 - 1000 $0.34 10000 $0.34	Buy Now
Rochester Electronics LLC CD74HCT109E IC FF JK TYPE DBL 1-BIT 16-PDIP
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CD74HCT109E	Tube	27,587		491	1 - 10 - 100 - 1000 $0.61 10000 $0.61	Buy Now
Rochester Electronics LLC CD74HCT10M IC GATE NAND 3CH 3-INP 14SOIC
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CD74HCT10M	Tube	21,437		449	1 - 10 - 100 - 1000 $0.67 10000 $0.67	Buy Now
Rochester Electronics LLC CD74HCT10M96 IC GATE NAND 3CH 3-INP 14SOIC
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CD74HCT10M96	Bulk	12,500		1,794	1 - 10 - 100 - 1000 - 10000 $0.17	Buy Now
Rochester Electronics LLC CD74HCT109M96 IC FF JK TYPE DBL 1-BIT 16-SOIC
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CD74HCT109M96	Bulk	12,500		624	1 - 10 - 100 - 1000 $0.48 10000 $0.48	Buy Now

Find more CD74HCT10 price and stock on Findchips.com

CD74HCT10 Datasheets (91)

Part	Manufacturer	Description	Datasheet Type	PDF	PDF Size	Page count
CD74HCT10	Texas Instruments	High Speed CMOS LogicTriple 3-Input NAND Gate	Original	PDF	32.55KB	6
CD74HCT10	Texas Instruments	High Speed CMOS Logic Triple 3-Input NAND Gate	Original	PDF	39.98KB	6
CD74HCT107	Texas Instruments	Dual J-K Flip-Flop with ResetNegative-Edge Trigger	Original	PDF	45.14KB	8
CD74HCT107	Texas Instruments	Dual J-K Flip-Flop with Reset Negative-Edge Trigger	Original	PDF	55.87KB	8
CD74HCT107E	Texas Instruments	CD74HCT107 - High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125	Original	PDF	630.46KB	16
CD74HCT107E	Texas Instruments	Dual J-K Flip-Flop with Reset Negative-Edge Trigger	Original	PDF	55.87KB	8
CD74HCT107E	Texas Instruments	High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125	Original	PDF	454.56KB	15
CD74HCT107E	Unknown	Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.	Historical	PDF	33.05KB	1
CD74HCT107E96	Texas Instruments	Dual J-K Flip-Flop with Reset Negative-Edge Trigger	Original	PDF	45.14KB	8
CD74HCT107EE4	Texas Instruments	CD74HCT107 - High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125	Original	PDF	630.46KB	16
CD74HCT107EE4	Texas Instruments	High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset	Original	PDF	290.99KB	13
CD74HCT107EE4	Texas Instruments	High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125	Original	PDF	454.56KB	15
CD74HCT107EG4	Texas Instruments	Integrated Circuits (ICs) - Logic - Flip Flops - IC FF JK TYPE DUAL 1BIT 14DIP	Original	PDF	632.95KB
CD74HCT107M	Unknown	Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.	Historical	PDF	33.05KB	1

CD74HCT109	Texas Instruments	High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset	Original	PDF	46.64KB	8
CD74HCT109	Texas Instruments	Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger	Original	PDF	57.17KB	8
CD74HCT109E	Texas Instruments	CD74HCT109 - High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125	Original	PDF	440.61KB	16
CD74HCT109E	Texas Instruments	HIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET	Original	PDF	57.16KB	8
CD74HCT109E	Texas Instruments	Dual J-inverted K Flip-Flop with Set and Reset Positive-Edge Trigger	Original	PDF	155.36KB	11
CD74HCT109E	Texas Instruments	High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125	Original	PDF	457.52KB	15

CD74HCT10 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
HC10 Abstract: CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HCT10 Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, CD54HCT10, CD74HCT10	Original	HCT10 CD54HC10, CD74HC10, CD54HCT10, CD74HCT10 SCHS128C HCT10 HC10 CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10	PDF
Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140C Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised May 2003	Original	CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 SCHS140C HC109 HCT109 CD74H CT109)	PDF
Contextual Info: CD74HC107, CD74HCT107 ^ Texas In s t r u m e n t s Data sheet acquired from Harris Sem iconductor SCHS139 Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 Features Description • Hysteresis on Clock Inputs for Improved Noise Immu nity and Increased Input Rise and Fall Times	OCR Scan	CD74HC107, CD74HCT107 CD74HC107 CD74HCT107 HC/HCT73	PDF
HC107 Abstract: 74HCT 74LS CD74HC107 CD74HC107E CD74HCT107 CD74HCT107E HCT10 Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD74HC107, CD74HCT107 Data sheet acquired from Harris Semiconductor SCHS139 Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 Features Description • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times	Original	HC107 HCT10 CD74HC107, CD74HCT107 SCHS139 CD74HC107 CD74HCT107 HC107 74HCT 74LS CD74HC107E CD74HCT107E HCT10	PDF
Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, CD54HCT10, CD74HCT10	Original	CD54HC10, CD74HC10, CD54HCT10, CD74HCT10 SCHS128C HCT10 HCT10	PDF
HCT10 Abstract: CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HC10 Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, CD54HCT10, CD74HCT10	Original	HCT10 CD54HC10, CD74HC10, CD54HCT10, CD74HCT10 SCHS128C HCT10 CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HC10	PDF
CD54HC107 Abstract: CD54HC107F3A CD74HC107 CD74HC107E CD74HC107M CD74HCT107 HC107 HCT10 Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54HC107, CD74HC107, CD74HCT107 Data sheet acquired from Harris Semiconductor SCHS139D Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised October 2003	Original	HC107 HCT10 CD54HC107, CD74HC107, CD74HCT107 SCHS139D HC107 CD74HCT107 CD54HC107 CD54HC107F3A CD74HC107 CD74HC107E CD74HC107M HCT10	PDF
CD54HC10 Abstract: CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HC10 HCT10 Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, CD54HCT10, CD74HCT10	Original	HCT10 CD54HC10, CD74HC10, CD54HCT10, CD74HCT10 SCHS128C HCT10 CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HC10	PDF
Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54HC107, CD74HC107, CD74HCT107 Data sheet acquired from Harris Semiconductor SCHS139D Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised October 2003	Original	CD54HC107, CD74HC107, CD74HCT107 SCHS139D HC107 CD74HCT107 HC/HCT73	PDF
Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140E Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised October 2003	Original	CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 SCHS140E HC109 HCT109 CD74H CT109)	PDF
Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140E Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised October 2003	Original	CD74H CT109) CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 SCHS140E HC109 HCT109	PDF
"J-K Flip flop" Abstract: CD54HC107F3A HC107 T flip flop IC CD54HC107 CD74HC107 CD74HC107E CD74HC107M CD74HCT107 HCT10 Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54HC107, CD74HC107, CD74HCT107 Data sheet acquired from Harris Semiconductor SCHS139D Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised October 2003	Original	HC107 HCT10 CD54HC107, CD74HC107, CD74HCT107 SCHS139D HC107 CD74HCT107 "J-K Flip flop" CD54HC107F3A T flip flop IC CD54HC107 CD74HC107 CD74HC107E CD74HC107M HCT10	PDF
HC107 Abstract: CD54HC107 CD54HC107F3A CD74HC107 CD74HC107E CD74HC107M CD74HCT107 HCT10 Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54HC107, CD74HC107, CD74HCT107 Data sheet acquired from Harris Semiconductor SCHS139C Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised May 2003	Original	HC107 HCT10 CD54HC107, CD74HC107, CD74HCT107 SCHS139C HC107 CD74HCT107 CD54HC107 CD54HC107F3A CD74HC107 CD74HC107E CD74HC107M HCT10	PDF
CD54HC10 Abstract: CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HC10 HCT10 Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, CD54HCT10, CD74HCT10	Original	HCT10 CD54HC10, CD74HC10, CD54HCT10, CD74HCT10 SCHS128B HCT10 CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HC10	PDF

C109 Abstract: CD54HC109 CD54HC109F3A CD54HCT109 CD74HC109 CD74HCT109 HC109 Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140E Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised October 2003	Original	CD74H CT109) CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 SCHS140E HC109 HCT109 C109 CD54HC109 CD54HC109F3A CD54HCT109 CD74HC109 CD74HCT109	PDF
C109 Abstract: CD54HC109 CD54HC109F3A CD54HCT109 CD74HC109 CD74HCT109 HC109 Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140E Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised October 2003	Original	CD74H CT109) CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 SCHS140E HC109 HCT109 C109 CD54HC109 CD54HC109F3A CD54HCT109 CD74HC109 CD74HCT109	PDF
C109 Abstract: CD54HC109 CD54HC109F3A CD54HCT109 CD74HC109 CD74HCT109 HC109 Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140D Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised July 2003	Original	CD74H CT109) CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 SCHS140D HC109 HCT109 C109 CD54HC109 CD54HC109F3A CD54HCT109 CD74HC109 CD74HCT109	PDF
D74HC10 Contextual Info: CD74HC10,0 h a r r is S E M I C O N D U C T O R High Speed CMOS Logic Triple 3-lnput NAND Gate August 1997 Features Description • Buffered Inputs The Harris CD74HC10, CD74HCT10, logic gates utilize silicon gate CMOS technology to achieve operating speeds	OCR Scan	CD74HC10, CD74HCT10, 74HCT 1-800-4-HARRIS D74HC10	PDF
CD74HC10E Abstract: CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HCT10 HC10 HCT10 Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, CD54HCT10, CD74HCT10	Original	HCT10 CD54HC10, CD74HC10, CD54HCT10, CD74HCT10 SCHS128C HCT10 CD74HC10E CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HCT10 HC10	PDF
Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140E Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised October 2003	Original	CD74H CT109) CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 SCHS140E HC109 HCT109	PDF
Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140E Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised October 2003	Original	CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 SCHS140E HC109 HCT109 CD74H CT109)	PDF
Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140E Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised October 2003	Original	CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 SCHS140E HC109 HCT109 CD74H CT109)	PDF
Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, CD54HCT10, CD74HCT10	Original	HCT10 CD54HC10, CD74HC10, CD54HCT10, CD74HCT10 SCHS128C HCT10	PDF
74LS family Abstract: HCT73 Contextual Info: ASSESS? CD74HC107, CD74HCT107 Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 Features Description • Hysteresis on Clock Inputs for Improved Noise Immu nity and Increased Input Rise and Fall Times The Harris CD74HC107 and CD74HCT107 utilize silicon	OCR Scan	CD74HC107, CD74HCT107 CD74HC107 CD74HCT107 HC/HCT73 74HCT 74LS family HCT73	PDF

CD74HCT10 Search Results

CD74HCT10 Result Highlights (5)

CD74HCT10 Price and Stock

Rochester Electronics LLC CD74HCT10E

Rochester Electronics LLC CD74HCT109E

Rochester Electronics LLC CD74HCT10M

Rochester Electronics LLC CD74HCT10M96

Rochester Electronics LLC CD74HCT109M96

CD74HCT10 Datasheets (91)

CD74HCT10 Datasheets Context Search

HC10

HC107

HCT10

CD54HC107

CD54HC10

"J-K Flip flop"

HC107

CD54HC10

C109

C109

C109

D74HC10

CD74HC10E

74LS family