CI 74804 Search Results

CI 16551

Abstract: Harris CMOS Integrated Circuits
Contextual Info: CD74HCU04 CI, INPUT CAPACITANCE pF Typical Performance Curves 70 65 60 55 50 45 40 35 30 25 20 15 10 5 (Continued) AMBIENT TEMPERATURE, TA = 25oC VDD = 2V, VI 0-2V INPUT PIN 5 CONDITIONS VDD = 3V, VI 0-3V VDD = 4V, VI 0-4V VDD = 5V, VI 0-5V VDD = 6V, VI 0-6V

Contextual Info: hS E M aI C O rN DrU Ci TsO R "F S F 2 5 4mD J, F m S F u 2 5 4 a mR m Radiation Hardened, SEGR Resistant N-Channel Power MOSFETs Features Package • 18A, 250V, rDS ON = 0.170£1 TO-254AA • Total Dose - M eets Pre-Rad Specifications to 100kRAD(Si) • Single Event

IN402

Contextual Info: DG406/883, DG407/883 HARRIS S E M I C O N D U C T O R Single 16-Channel/Differential 8-Channel C M O S Analog Multiplexers April 1997 Features Description • Thi s Ci rcui t is Pr o c e s s e d in A c c o r d a n c e to M I L - S T D - 8 8 3 and is Ful l y

BASIC digital multimeter diagram

Abstract: PKM24-4A0 38D8R02H 5 VOLT piezo beeper 4MC2 harris volt meter digital multimeter icl7139
Contextual Info: h S E M aI C O r N Dr U Ci T sO R æ Im C L m m 7 1m 3 m 9 w , Features • 18 R a n g e s -IC L 7 1 49 4 2 4 4 4 C L 7a ^ m 1* 4 * 9 Description 13 R a n g e s - ICL7139 - 4 DC Voltage 400mV, 4 V, 40V, 400V - 1 AC Voltage 400V - 4 DC Current 4mA, 40mA, 400mA, 4A

cd74hc32

Abstract: CD74HCT32
Contextual Info: CD54HCT32, CD74HC32, CD74HCT32 S E M I C O N D U C T O R High Speed CMOS Logic Quad 2-Input OR Gate September 1997 Features Description • Typical Propagation Delay: 7ns at VCC = 5V, CL = 15pF, TA = 25oC The Harris CD74HC32, CD74HCT32 contain four 2-input OR

IC 3914

Abstract: CD54AC541F3A CD54ACT541F3A
Contextual Info: CD54AC541F3A, CD54ACT541F3A S E M I C O N D U C T O R Octal Buffer/Line Driver Three-State, Non-Inverting July 1998 Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1.

CD74HCT132 harris

Abstract: CD74HC132 CD74HCT132
Contextual Info: CD74HC132, CD74HCT132 S E M I C O N D U C T O R High Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger August 1997 Features Description • Unlimited Input Rise and Fall Times The Harris CD74HC132, CD74HCT132 each contain four 2-input NAND Schmitt Triggers in one package. This logic

Contextual Info: HS-1115RH S Radiation Hardened, High Speed, Low Power Output Limiting, Closed-Loop-Buffer Amplifier August 1996 Features Description • Electrically Screened to SMD 5962F9678501VPA The HS-1115RH is a radiation hardened, high speed closed loop buffer featuring both user programmable gain and out­

XF MR 60hz trans

Abstract: VB26
Contextual Info: HC-5509B3999-003 SLIC S u b s c r ib e r Line Interface Circuit March 1996 Features Description • Dl Monolithic High Voltage Process • Selective Power Denial to Subscriber The HC-5509B3999-003 telephone Subscriber Line Inter­ face Circuit integrates most of the BORSCHT functions on a

cd74hc240

Contextual Info: CD74HC240, CD74HCT240, CD74HC241, CD74HCT241, CD74HC244, CD74HCT244 S E M I C O N D U C T O R High Speed CMOS Logic Octal Buffer/Line Drivers, Three-State November 1997 Features Description • CD74HC/HCT240 Inverting The Harris CD74HC240 and CD74HCT240 are inverting

CD74HC86

Abstract: 74HCT 74LS CD54HC86W CD54HCT86W CD74HC86E CD74HC86M CD74HCT86 CD74HCT86E CD74HCT86M
Contextual Info: CD74HC86, CD74HCT86 S E M I C O N D U C T O R High Speed CMOS Logic Quad 2-Input EXCLUSIVE OR Gate August 1997 Features Description • Typical Propagation Delay: 9ns at VCC = 5V, CL = 15pF, TA = 25oC The Harris CD74HC86, CD74HCT86 contain four independent EXCLUSIVE OR gates in one package. They

Contextual Info: CD74HC73, CD74HCT73 S E M I C O N D U C T O R Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 Features Description • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times The Harris CD74HC73 and CD74HCT73 utilize silicon gate

cd74hc10e

Abstract: cd74hct10
Contextual Info: CD74HC10, CD74HCT10 S E M I C O N D U C T O R High Speed CMOS Logic Triple 3-Input NAND Gate August 1997 Features Description • Buffered Inputs The Harris CD74HC10, CD74HCT10, logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of

74LS series logic gate symbols

Abstract: 74HCT 74LS CD54HC20W CD74HC20 CD74HC20E CD74HC20M CD74HCT20 CD74HCT20E CD74HCT20M
Contextual Info: CD74HC20, CD74HCT20 S E M I C O N D U C T O R High Speed CMOS Logic Dual 4-Input NAND Gate August 1997 Features Description • Buffered Inputs The Harris CD74HC20, CD74HCT20, logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of

cd74hc107

Contextual Info: CD74HC107, CD74HCT107 S E M I C O N D U C T O R Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 Features Description • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times The Harris CD74HC107 and CD74HCT107 utilize silicon

CD74HCT75

Abstract: CD74HC75 CD74HCT75 Harris
Contextual Info: CD74HC75, CD74HCT75 S E M I C O N D U C T O R Dual 2-Bit Bistable Transparent Latch March 1998 Features Description • True and Complementary Outputs The Harris CD74HC75 and CD74HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is

cd74hc74

Abstract: CD74HCT74
Contextual Info: CD54HC74, CD74HC74, CD74HCT74 S E M I C O N D U C T O R Dual D Flip-Flop with Set and Reset Positive-Edge Trigger January 1998 Features Description • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times The Harris CD54HC74, CD74HC74 and CD74HCT74 utilize

74ls gate symbols

Abstract: CD74HC21 74HCT 74LS CD74HC21E CD74HC21M CD74HCT21 CD74HCT21E CD74HCT21M cd74hct21 harris
Contextual Info: CD74HC21, CD74HCT21 S E M I C O N D U C T O R High Speed CMOS Logic Dual 4-Input AND Gate August 1997 Features Description • Buffered Inputs The Harris CD74HC21, CD74HCT21, logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of

Contextual Info: HIN232A HARRIS S E M I C O N D U C T O R High Speed +5V RS-232 Transm itter/R eceiver w ith 0.1 M icrofarad External C apacitor juiy 1997 Features Description • Meets All EIA RS-232E and V.28/V.24 Specifications The HIN232A High Speed RS-232 transmitter/receiver

cd74hc4351

Contextual Info: S E M I C O N D U C T O R CD74HC4351, CD74HCT4351, CD74HC4352 High Speed CMOS Logic Analog Multiplexers/Demultiplexers with Latch February 1998 FeaturesHI3306EVAL Description • Wide Analog Input Voltage Range . . . . . . . . . ±5V Max The Harris CD74HC4351,

cd74hct563

Contextual Info: S E M I C O N D U C T O R CD74HC533, CD74HCT533, CD74HC563, CD74HCT563 January 1998 High Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs Features Description • Common Latch-Enable Control The Harris CD74HC533, CD74HCT533, CD74HC563, and

cd74hc67

Contextual Info: CD74HC670, CD74HCT670 S E M I C O N D U C T O R High-Speed CMOS Logic 4x4 Register File January 1998 Features Description • Simultaneous and Independent Read and Write Operations The Harris CD74HC670 and CD74HCT670 are 16-bit register files organized as 4 words x 4 bits each. Read and write

max5519

Contextual Info: CD74HC597, CD74HCT597 S E M I C O N D U C T O R High Speed CMOS Logic 8-Bit Shift Register with Input Storage January 1998 Features Description • Buffered Inputs The Harris CD74HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin-compatible with the

CD74HC259 harris

Contextual Info: CD74HC259, CD74HCT259 S E M I C O N D U C T O R High Speed CMOS Logic 8-Bit Addressable Latch November 1997 Features Description • Buffered Inputs and Outputs The Harris CD74HC259 and CD74HCT259 Addressable Latch features the low-power consumption associated with