CML VTERM Search Results

CML ECL termination

Abstract: AND8173 AND8020
Contextual Info: AND8173/D Termination and Interface of On Semiconductor ECL Devices With CML Current Mode Logic OUTPUT Structure http://onsemi.com APPLICATION NOTE By Paul Shockman Contents SECTION 1.UNLOADED CML VOLTAGE LEVELS (DC OPEN) SECTION 2.DIRECT CONNECT (DC) CML LOAD

AND8020

Abstract: CML ECL termination Z0 127 TRANSISTOR equivalent
Contextual Info: AND8173/D Termination and Interface of ON Semiconductor ECL Devices With CML Current Mode Logic OUTPUT Structure http://onsemi.com APPLICATION NOTE By Paul Shockman Introduction Contents SECTION 1.UNLOADED CML VOLTAGE LEVELS (DC OPEN) SECTION 2.DIRECT CONNECT (DC) CML LOAD

CML buffer

Abstract: zn470 ORSO42G5 ORSO82G5 ORT42G5 ORT82G5 quad resistor 470 ohm
Contextual Info: FPSC SERDES CML Buffer Interface July 2003 Technical Note TN1029 Introduction This document discusses the high-speed serial buffers provided in Lattice’s ORT82G5, ORT42G5, ORSO82G5 and ORSO42G5 FPSC devices. These current mode logic CML buffers are part of a second generation Quad

SN65LVDS100 Application Report

Abstract: CDC111 CDCLVP110 CDCVF111 SN65LVDS101 SN65LVDT100 SN65LVDT33 SLLA101 sn65lvds CML100
Contextual Info: Application Report SCAA059C – March 2003 – Revised October 2007 AC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML Kal Mustafa/Chris Sterzik. High Performance Analog

SLLA101

Abstract: CML ECL termination EZ 644 rs-422 TO lvds SN65LVDS108
Contextual Info: Application Report SLLA101 - May 2001 Interfacing Different Logic With LVDS Receivers Chris Sterzik Data Transmission ABSTRACT This application report provides explanations and design considerations for interfacing RS–422, differential current mode logic CML , differential emitter coupled logic (ECL), and

SLLA101

Abstract: CML ECL termination rs-422 TO lvds SN65LVDS108
Contextual Info: Application Report SLLA101 - September 2001 Interfacing Different Logic With LVDS Receivers Chris Sterzik Data Transmission ABSTRACT This application report provides explanations and design considerations for interfacing RS–422, differential current mode logic CML , differential emitter coupled logic (ECL), and

SLLA120

Abstract: TLK1201 SN65LVDS9x SLK2501 SLK2511 TLK3114SA pecl logic voltage levels TLK1501 TLK2201 TLK2501
Contextual Info: Application Report SLLA120 - December 2002 Interfacing Between LVPECL, VML, CML, and LVDS Levels Serial Gigabit Solutions Nick Holland ABSTRACT This application report introduces the various interface standards used today in modern telecom and datacom systems and describes the methods used to interface between similar

sdh S 4.1

Abstract: CB50-1206 STM-16 VSC8121
Contextual Info: VITESSE SEMICONDUCTOR CORPORATION Data Sheet 2.488GHz SONET/SDH Clock Generator VSC8121 Features • Monolithic Phase Locked Loop • Jitter Meets SONET OC-48 and SDH STM-16 Requirements • On-Chip LC Oscillator • High Speed CML Clock Output • On-Chip Loop Filter

TDK-CB50-1206

Abstract: u 741 u741 STM-16 VSC8121 30 pin FRC CON vitesse oscillator 77.76mhz
Contextual Info: VITESSE SEMICONDUCTOR CORPORATION Data Sheet 2.488GHz SONET/SDH Clock Generator VSC8121 Features • Monolithic Phase Locked Loop • Jitter Meets SONET OC-48 and SDH STM-16 Requirements • On-Chip LC Oscillator • High-Speed CML Clock Output • On-Chip Loop Filter

VSC9182

Contextual Info: VSC9182 Data Sheet 64x64 STS-12/STM-4 TSI Switch Fabric FEATURES • 64x64 STS-12/STM-4 TSI Switch with Nonblocking 768x768 STS-1 Switch Matrix • Supports Both Multicast and Broadcast • Serial LVDS 622Mb/s High-Speed Interface with PECL/CML Compatibility and Retiming

e5027

Abstract: BYT 70 VT221 sgi01 E4110 march networks stm-5 gif11 E1110 327-o E9110
Contextual Info: VTXP-24 Device 1.25 Gbps Virtual Tributary Processor with Integrated VT/STS & VC/AU3 Switch TXC-06970 DATA SHEET PRODUCT PREVIEW TXC-06970-MB, Ed. 2 March 2006 FEATURES • Line or Client interfaces - Dual CML 2.488 Gbit/s TFI-5 compliant shared with terminal and interconnect interfaces

Contextual Info: VTXP-48 Device 2.5 Gbps Virtual tributary Processor with Integrated 45 Gbps VT/STS & VC/AU3 Switch TXC-06960 DATA SHEET PRODUCT PREVIEW TXC-06960-MB, Ed. 2 March 2006 FEATURES • Line or Client interfaces - Dual CML 2.488 Gbit/s TFI-5 compliant shared with terminal and inter-connect interfaces

CML Vterm

Abstract: CDC111 CDCLVD110 CDCLVP110 CDCVF111 SN65LVDS101 SN65LVDT100 SN65LVDT122 SN65LVDT33 SN64LVDS33
Contextual Info: Application Report SCAA059 – March 2003 AC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML Kal Mustafa/Chris Sterzik High Performance Analog ABSTRACT This report provides a quick reference of ac-coupling techniques for interfacing between different logic levels. The four differential signaling levels found in this report are lowvoltage positive-referenced emitter coupled logic LVPECL , low-voltage differential

Si53320

Abstract: si5332
Contextual Info: Si53320 1:5 L O W J I T T E R LVPECL C LOCK B UFFER W I T H 2:1 I NPUT M UX Features         5 LVPECL outputs  Ultra-low additive jitter: 100 fs rms  Wide frequency range: 1 to 725 MHz  Input compatible with LVPECL, LVDS, CML, HCSL, LVCMOS

Contextual Info: VITESSE SEMICONDUCTOR CORPORATION Target Specification 2.488 Gb/s Quad Data Re-timer VSC8124 Features • Four Channel 2.488 Gb/s Data Recovery • Differential on Chip Terminated Serial Data I/O • SONET Quality Jitter Tolerance • Bypass for OC3, OC12 Data Rates

VSC8124

Contextual Info: VITESSE SEMICONDUCTOR CORPORATION Target Specification 2.488 Gb/s Quad Data Re-timer VSC8124 Features • Four Channel 2.488 Gb/s Data Recovery • Differential on Chip Terminated Serial Data I/O • SONET Quality Jitter Tolerance • Bypass for OC3, OC12 Data Rates

MO-220 7x7 0.4 pitch

Abstract: si5331 Si53313
Contextual Info: Si53313 D UAL 1:5 L OW J I T T E R B UFFER / L EVEL T RANSLATOR <1.25 GH Z Features        10 differential or 20 LVCMOS outputs Ultra-low additive jitter: 100 fs rms  Wide frequency range: 1 MHz to 1.25 GHz  Any-format input with pin selectable

Si53303

Contextual Info: Si53303 D UAL 1:5 L OW J I T T E R B UFFER / L EVEL T RANSLATOR Features         10 differential or 20 LVCMOS outputs Ultra-low additive jitter: 100 fs rms Wide frequency range: 1 to 725 MHz Any-format input with pin selectable

ecl 806

Abstract: CML ECL termination PLE 2 - 25va Vterm pecl logic voltage levels
Contextual Info: Application Note 806 LVPECL, PECL, ECL Logic and Termination March 2009 by: Ken Johnson and Bob Gubser ABSTRACT This application note will highlight characteristics of Pletronics Low Voltage Positive Emitter Coupled Logic LVPECL frequency control products and provide guidance for

Si53304

Contextual Info: Si53304 1:6 L OW J I T T E R U NIVERSAL B U F F E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX A N D I NDIVIDUAL OE Features         6 differential or 12 LVCMOS outputs  Ultra-low additive jitter: 100 fs rms  Wide frequency range: 1 to 725 MHz

Si53314

Abstract: in 5007
Contextual Info: Si53314 1 : 6 L O W J IT TE R U N I V E R S A L B U FF E R / L E V E L T R A N S L A T O R W IT H 2 : 1 I N P U T M U X A N D I N D I V I D U A L O E < 1 . 2 5 G H Z Features        6 differential or 12 LVCMOS outputs  Ultra-low additive jitter: 100 fs rms 

RJL-ST11H-SO51

Abstract: Stratos st11 3 PORT 10 100 ETHERNET TRANSCEIVER MIL-STK-ST31M
Contextual Info: MIL-SxK-ST11x DC Coupled MIL-SxK-ST31x (AC Coupled) MIL-SxK-ST41x (DC Coupled, Jam) MIL-SxK-ST61x (AC Coupled, Jam) MILITARY SFF OPTICAL TRANSCEIVER Gigabit Ethernet / 1x Fibre Channel Applications 3.3V, 850nm VCSEL, Multimode, Up to 550M APPLICATIONS FEATURES

Si53315

Abstract: 44qfn
Contextual Info: Si53315 1 : 1 0 L O W J I TT E R U N I V E R S A L B U F F E R /L E V E L T R A N S L A T O R W IT H 2 : 1 I N P U T M U X A N D I N D I V I D U A L O E < 1 . 2 5 G H Z Features         10 differential or 20 LVCMOS outputs Ultra-low additive jitter: 100 fs rms

rs 422

Abstract: Si53312
Contextual Info: Si53312 1 : 1 0 L OW J I T T E R U NIVERSAL B U FF E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX <1.25 GH Z Features Ordering Information: See page 25. Applications Q6 Q6 VDDOB 34 37 35 38 39 DIVA 1 33 DIVB SFOUTA[1] SFOUTA[0] 2 32 3 31 SFOUTB[1] SFOUTB[0]