CY7B99X0 Search Results

CY7B9910

Abstract: CY7B9920
Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Features • • • • • • • • • Block Diagram Description All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation Zero input to output delay 50% duty-cycle outputs Outputs drive 50Ω terminated lines

CY7B9910

Abstract: CY7B9920
Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Features • All outputs skew <100 ps typical 250 max. ■ 15 to 80 MHz output operation ■ Zero input to output delay The completely integrated PLL enables “zero delay” capability. External divide capability, combined with the internal PLL, allows

Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Features • All outputs skew <100 ps typical 250 max. ■ 15 to 80 MHz output operation ■ Zero input to output delay The completely integrated PLL enables “zero delay” capability. External divide capability, combined with the internal PLL, allows

Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Low Skew Clock Buffer Features Block Diagram Description • All outputs skew < 100 ps typical 250 max Phase Frequency Detector and Filter ■ 15 to 80 MHz output operation ■ Zero input to output delay ■ 50% duty cycle outputs

CY7B9910

Abstract: CY7B9920
Contextual Info: CY7B9910 CY7B9920 W ances as low as 50 while delivering miniĆ mal and specified output skews and fullĆ swing logic levels CY7B9910 TTL or CY7B9920 CMOS . Features D All outputs skew <100 ps typical (250 max.) D D D D D D D 15Ć to 80ĆMHz output operation

CY7B9910

Abstract: CY7B9920 BUT12
Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Low Skew Clock Buffer Features Block Diagram Description • All outputs skew < 100 ps typical 250 max Phase Frequency Detector and Filter ■ 15 to 80 MHz output operation ■ Zero input to output delay ■ 50% duty cycle outputs

Contextual Info: pyi Low Skew Tm\ ^ QS59920 PLL Clock Driver Sem iconductor, Inc. T u rb o Q o c K ' p r e l im in a r y J r . FEATURES/BENEFITS DESCRIPTION • 8 zero delay outputs • Low skew: 200ps same pair, 250ps all outputs • Selectable positive or negative edge synchronization

Contextual Info: L0WSkew PLL Clock Driver S5992S advance T u rb O d O C k " J r. Q u a lit y S e m ic o n d u c t o r , I n c . INFORMATION FEATURES/BENEFITS DESCRIPTION • 8 zero delay outputs • Low skew: 200ps same pair, 250ps all outputs • Selectable positive or negative edge

Contextual Info: 1 Q uality Semiconductor , I nc . QS59910 QS59920 Low Skew PLL Clock Driver TurboClock Jr. FEATURES/BENEFITS DESCRIPTION • 8 zero delay outputs • Selectable positive or negative edge synchronization • Synchronous output enable • Output frequency: 15MHz to 110MHz

TP 401-400

Abstract: CY7B9910 CY7B9920 QS59910 QS59920
Contextual Info: ff i ^ q u a l it y Low Skew PLL Clock Driver SifiSIS QS59920 advance TurboClock Jr. in f o r m a t io n S e m ic o n d u c t o r , I n c . FEATURES/BENEFITS DESCRIPTION • 8 zero delay outputs • Low skew: 200ps same pair, 250ps all outputs • Selectable positive or negative edge

Contextual Info: fax id: 3516 CY7B9910 CY7B9920 Low Skew Clock Buffer Block Diagram Description Featu res Phase Frequency Detector and Filter • All outputs skew <100 ps typical 250 max. • 1 5 -to 80-MHz output operation These two blocks accept inputs from the reference frequency

Contextual Info: CY7B9910 CY7B9920 PRELIMINARY Low Skew Clock Buffer Features • All outputs skew <100 ps typical 250 max. ■ 15 to 80 MHz output operation ■ Zero input to output delay The completely integrated PLL enables “zero delay” capability. External divide capability, combined with the internal PLL, allows

CY7B9910

Abstract: CY7B9920
Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Features Block Diagram Description • All Outputs Skew <100 ps typical 250 max. Phase Frequency Detector and Filter ■ 15 to 80 MHz Output Operation ■ Zero Input to Output Delay ■ 50% Duty Cycle Outputs ■ Outputs drive 50Ω terminated lines

CY7B9910

Abstract: CY7B9920 QS59910 QS59920
Contextual Info: QS59910, QS59920 QS59910 QS59920 Low Skew PLL Clock Driver TurboClock Jr. Q QUALITY SEMICONDUCTOR, INC. FEATURES/BENEFITS DESCRIPTION • 8 zero delay outputs • Selectable positive or negative edge synchronization • Synchronous output enable • Output frequency: 15MHz to 110MHz

Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Low Skew Clock Buffer Features Block Diagram Description • All outputs skew < 100 ps typical 250 max Phase Frequency Detector and Filter ■ 15 to 80 MHz output operation ■ Zero input to output delay ■ 50% duty cycle outputs

Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Features Block Diagram Description • All Outputs Skew <100 ps typical 250 max. Phase Frequency Detector and Filter ■ 15 to 80 MHz Output Operation ■ Zero Input to Output Delay ■ 50% Duty Cycle Outputs ■ Outputs drive 50Ω terminated lines

CY7B9910

Abstract: CY7B9920
Contextual Info: fax id: 3516 1CY 7B9 92 0 CY7B9910 CY7B9920 Low Skew Clock Buffer Features • • • • • • • • • Block Diagram Description All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation Zero input to output delay 50% duty-cycle outputs

Contextual Info: Q Q u a l it y S e m ic o n d u c t o r , I n c . QS59910 QS59920 Low Skew PLL Clock Driver TurboClock Jr. FEATURES/BENEFITS DESCRIPTION • 8 zero delay outputs • Selectable positive or negative edge synchronization • Synchronous output enable • Output frequency: 15MHz to 110MHz

Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Features • • • • • • • • • Block Diagram Description All outputs skew <100 ps typical 250 max. 1 5 -to 80-MHz output operation Zero input to output delay 50% duty-cycle outputs O utputs drive 50& term inated lines

Contextual Info: Low Skew PLL Clock Driver wgy Tm\ Qmim QS59920 advance TurboClock Jr. in fo rm a tio n S e m ic o n d u c t o r , I n c . FEATURES/BENEFITS DESCRIPTION • 8 zero delay outputs • Low skew: 200ps same pair, 250ps all outputs • Selectable positive or negative edge