CY7C1512 Search Results

Contextual Info: CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 兆2-Mb典t唯Q当R 唯存存唯止RAM唯2唯 • ■ J正AG唯114版.1唯 ■ 唯样PLL核 ❐ ■ 350唯M字争唯 唯2唯 ■ ■ 唯样当当R核唯 唯 唯兆00唯M字争唯 K唯 ■ ❐ 唯K 唯350 M字争

CY7C1510AV18

Abstract: CY7C1512AV18 CY7C1514AV18 CY7C1525AV18 CY7C1512AV18-167BZXC
Contextual Info: CY7C1510AV18, CY7C1525AV18 CY7C1512AV18, CY7C1514AV18 72-Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1510AV18 – 8M x 8 ■ 250 MHz clock for high bandwidth

CY7C1512V18-250BZXC

Abstract: CY7C1510V18 CY7C1512V18 CY7C1514V18 CY7C1525V18
Contextual Info: CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 72-Mbit QDR -II SRAM 2-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth

350bz

Contextual Info: CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit QDR II SRAM 2-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1510KV18 – 8M x 8 ■ 350 MHz Clock for High Bandwidth

Contextual Info: CY7C1510JV18, CY7C1525JV18 CY7C1512JV18, CY7C1514JV18 72-Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions ■ 267 MHz Clock for High Bandwidth ■

CY7C1512JV18

Abstract: CY7C1514JV18 CY7C1525JV18
Contextual Info: CY7C1525JV18 CY7C1512JV18 CY7C1514JV18 72-Mbit QDR II SRAM 2-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions ■ 267 MHz Clock for High Bandwidth CY7C1525JV18 – 8M x 9

CY7C1510V18

Abstract: CY7C1512V18 CY7C1514V18
Contextual Info: CY7C1512V18 CY7C1514V18 72 Mbit QDR II SRAM Two Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for High Bandwidth ■ 2 word burst on all accesses

CY7C1512KV18-250BZXI

Contextual Info: CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit QDR II SRAM 2-Word Burst Architecture 72-Mbit QDR® II SRAM 2-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions

Contextual Info: CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 72-Mbit QDR II SRAM Two-Word Burst Architecture 72-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1525KV18 – 8 M x 9

CY7C1512KV18-250BZXC

Abstract: CY7C1512KV18-250BZC CY7C1525KV18-250BZXC MO-216
Contextual Info: CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit QDR II SRAM 2-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1510KV18 – 8M x 8 ■ 333 MHz Clock for High Bandwidth

7C15121

Abstract: CY7C1512-25SC CY7C1512 CY7C1512-15SC CY7C1512-15ZC CY7C1512-20SC CY7C1512-20ZI
Contextual Info: 1CY 7C15 12 PRELIMINARY CY7C1512 64K x 8 Static RAM Features • High speed — tAA = 15 ns • CMOS for optimum speed/power • Low active power — 770 mW • Low standby power — 28 mW • Automatic power-down when deselected • TTL-compatible inputs and outputs

Contextual Info: PRELIMINARY CY7C1512 64K x 8 Static RAM Features and three-state drivers. This device has an automatic pow­ er-down feature that reduces power consumption by more than 75% when deselected. • High speed — tAA = 15ns Writing to the device is accomplished by taking chip enable

CY7C1514KV18-333BZI

Abstract: CY7C1512KV18-300BZC
Contextual Info: CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit QDR II SRAM 2-Word Burst Architecture 72-Mbit QDR® II SRAM 2-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions

Contextual Info: CY7C1510V18 CY7C1512V18 CY7C1514V18 PRELIMINARY 72-Mbit QDR-II SRAM 2-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 300-MHz clock for high bandwidth • 2-Word Burst on all accesses

Contextual Info: THIS SPEC IS OBSOLETE Spec No: 001-06984 Spec Title: CY7C1512AV18/ CY7C1514AV18 72-MBIT QDR R II SRAM 2-WORD BURST ARCHITECTURE Sunset Owner: Jayasree Nayar (NJY) Replaced by: None CY7C1512AV18 CY7C1514AV18 72-Mbit QDR II SRAM 2-Word Burst Architecture

CY7C1512-25SC

Abstract: CY7C1512 CY7C1512-15SC CY7C1512-15ZC CY7C1512-20SC CY7C1512-20ZI 7C1512
Contextual Info: PRELIMINARY CY7C1512 64K x 8 Static RAM Features • High speed — tAA = 15 ns • CMOS for optimum speed/power • Low active power — 770 mW • Low standby power — 28 mW • Automatic power-down when deselected • TTL-compatible inputs and outputs

CY7C1514V18-250BZC

Abstract: CY7C1525V18-250BZC CY7C1510V18 CY7C1512V18 CY7C1514V18 CY7C1525V18
Contextual Info: CY7C1510V18 CY7C1525V18 CY7C1512V18 CY7C1514V18 PRELIMINARY 72-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 200-MHz clock for high bandwidth

Contextual Info: CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 72-Mbit QDR II SRAM Two-Word Burst Architecture 72-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1525KV18 – 8 M x 9

CY7C1512-25SC

Abstract: A12C A14C A15C CY7C1512
Contextual Info: ; PRELIMINARY CY7C1512 O i l h iib b 64K Features X 8 Static RAM and three -state drivers. T his de vice has an au tom atic po w ­ er-d ow n fea tu re tha t reduces po w e r con sum p tion by m ore than 75% w h en deselected. • High speed — tAA = 1 5 n s

Contextual Info: CY7C1512 P YP V «*1 i. X 64K X 8 Static RAM and three-state drivers. This device has an automatic pow­ er-down feature that reduces power consumption by more than 75% when deselected. Features • High s p e e d Writing to the device is accomplished by taking chip enable

Contextual Info: CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit QDR II SRAM 2-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1510KV18 – 8M x 8 ■ 333 MHz Clock for High Bandwidth

CY7C1512KV18-250BZXI

Abstract: CY7C1514KV18-300BZI CY7C1525KV18-167BZC
Contextual Info: CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1510KV18 – 8M x 8 ■ 333 MHz Clock for High Bandwidth

CY7C1510JV18

Abstract: CY7C1512JV18 CY7C1514JV18 CY7C1525JV18
Contextual Info: CY7C1510JV18, CY7C1525JV18 CY7C1512JV18, CY7C1514JV18 72-Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 267 MHz clock for high bandwidth ■

CY7C1510AV18

Abstract: CY7C1512AV18 CY7C1514AV18
Contextual Info: CY7C1512AV18 CY7C1514AV18 72-Mbit QDR II SRAM 2-Word Burst Architecture Features Configurations • Separate independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1512AV18 – 4M x 18 ■ 250 MHz Clock for high Bandwidth Functional Description