DS0035 Search Results

1575R-A

Abstract: 1575RA
Contextual Info: S E M IC O N D U C T O R 74F673A 16-Bit Serial-ln, Serial/P arallel-O ut Shift Register General Description Features The ’F673A contains a 16-bit serial-in, serial-out shift register and a 16-bit parallel-out storage register. A single pin serves either as an input for serial entry or as a 3-STATE serial out­

Receiver RXB6

Abstract: RXB6 RXB8 txc9 217-pin 8815 k RXB9 LU5X34F
Contextual Info: Preliminary Data Sheet July 2000 LU5X34F Quad Gigabit Ethernet Transceiver Overview The LU5X34F is a low-cost, low-power quad transceiver. It is used for data transmission over fiber or coaxial media in conformance with IEEE * 802.3z Gigabit Ethernet specification and Fibre Channel

transistor 5-2736

Abstract: 5-2736 data sheet ic 7495 pin diagram of ic 7495 pin diagram of ic 7495 A pin diagram of ic 7495 generator EN10 LU3X54FTL MR30 MR31
Contextual Info: Data Sheet July 2000 LU3X54FTL QUAD-FET for 10Base-T/100Base-TX/FX Introduction • Autopolarity detection and correction ■ Adjustable squelch level for extended line length capability two levels ■ Interfaces with IEEE 802.3u media independent interface (MII) or a serial 10 Mbits/s 7-pin interface

Contextual Info: Preliminary Data Sheet July 2000 LU5X31F Gigabit Ethernet Transceiver Overview Features The LU5X31F is a low-cost, low-power gigabit Ethernet transceiver. It is used for data transmission over fiber or coaxial media in conformance with IEEE* 802.3z Gigabit Ethernet specification and Fibre

Contextual Info: Preliminary Data Sheet July 2000 LU3X32FT Two-Port 3 V 10/100 Ethernet Transceiver TX/FX Note: For sustaining support only, not for new designs. • Built-in 10 Mbits/s transmit filter ■ 10 Mbits/s PLL exceeding tolerances for both preamble and data jitter

LU3X31FT-J80

Abstract: LU3X31FT Tx/Fx Media Converter LU3X31FTJ
Contextual Info: Preliminary Data Sheet July 2000 LU3X31FT Single-Port 3 V 10/100 Ethernet Transceiver TX/FX Overview The LU3X31FT is an integrated 10/100 Mbits/s physical layer device with an integrated transceiver. This part was designed for 10/100 Mbits/s applications where board space, cost, and power are at a premium and stringent functional interoperability is a

Contextual Info: S E M IC O N D U C T O R -n 74F273 Octal D Flip-Flop General Description Features The ’F273 has eight edge-triggered D-type flip-flops with in­ dividual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) inputs load and reset (clear) all

Contextual Info: S E M IC O N D U C T O R 74F779 8-Bit B idirectional Binary C ounter w ith 3-STATE O utputs General Description The ’F779 is a fully synchronous 8-stage up/down counter with multiplexed 3-STATE I/O ports for bus-oriented applica­ tions. All control functions hold, count up, count down, syn­

749 fairchild

Contextual Info: S E M I C O N D U C T O R -n 74F823 9-Bit D-Type Flip-Flop General Description Features The ’F823 is a 9-bit buffered register. It features Clock En­ able and Clear which are ideal for parity bus interfacing in high performance microprogramming systems.

Contextual Info: NOV 3 0 1992 A D C -H X , A D C -H Z S e rie s V 12-Bit, Analog-toDigital Converters INNOVATION AND EXCELLENCE FEATURES • 12-Bit resolution • 8-or 20-M icroseconds conversions • 5 Input ranges • Internal high Z buffer • Short-cycle operation GENERAL DESCRIPTION

LU5X31F

Contextual Info: Preliminary Data Sheet August 2000 LU5X31F Gigabit Ethernet Transceiver Overview Features The LU5X31F is a low-cost, low-power gigabit Ethernet transceiver. It is used for data transmission over fiber or coaxial media in conformance with IEEE* 802.3z Gigabit Ethernet specification and Fibre

str 2012

Abstract: PerkinElmer transformer PerkinElmer Optoelectronics tr-2012 PerkinElmer trigger thyristor aeg 50 kv pulse transformer
Contextual Info: TR-2012 EXTERNAL TRIGGER TRANSFORMER SF RED H E N 88 24" 610 MIN. V BEL D #22 TEF E 12" (305) MIN. 3 LEADS 0.38 (9.7) 2.06 (52.3) MAX. 0.19 (4.8) 66 HT PS DIMENSIONS ARE IN INCHES (MILLIMETERS) TR-2012 PF PF WEIGHT = 0.38 LB 1.00 (25.4) K BL SS BRN 1.75

LU3X31FT-J80

Abstract: LU3X31FT 4B5B decoder
Contextual Info: Preliminary Data Sheet March 2001 LU3X31FT Single-Port 3 V 10/100 Ethernet Transceiver TX/FX Overview The LU3X31FT is an integrated 10/100 Mbits/s physical layer device with an integrated transceiver. This part was designed for 10/100 Mbits/s applications

Contextual Info: S E M I C O N D U C T O R -n 74F398 • 74F399 Quad 2-Port Register General Description Features The ’ F398 and ’ F399 are the logical equivalents of a quad 2-input m ultiplexer feeding into fo u r edge-triggered flip-flops. A com m on S elect input determ ines w hich of the tw o 4-bit

100BASETFD

Abstract: ty940 5-2736 transistor 5-2736 LC10 LC100 LS10 LS100 LU6612 MR30
Contextual Info: Data Sheet July 2000 LU6612 FASTCAT TM Single-FET for 10Base-T/100Base-TX Features General 10 Mbits/s Transceiver • Autonegotiation IEEE 802.3u clause 28 : — Fast link pulse (FLP) burst generator — Arbitration function — Accepts preamble suppression

sa 57970

Abstract: MR20L LU3XS38FT-BA388 MR20 MR21 MR30 MR31 LU3XS38FT
Contextual Info: Preliminary Data Sheet July 2000 LU3XS38FT 8-Port 10/100 Ethernet Switch with Integrated PHY Overview The LU3XS38FT is a highly integrated, scalable 8-port 10/100 switch/MAC/PHY Ethernet standard product. This device supports both UTP and fiber on all ports. It is targeted for high performance and low

100BASE-X

Abstract: LU3X31T-T64 REF10 PCMCIA Ethernet
Contextual Info: Preliminary Data Sheet July 2000 LU3X31T-T64 Single-Port 3 V 10/100 Ethernet Transceiver TX Overview The LU3X31T-T64 is a fully integrated 10/100 Mbits/s physical layer device with an integrated transceiver. It is provided in a 64-pin TQFP package with low-power operation and powerdown

5-2736

Abstract: LU3X51FT transistor 5-2736 MR30 MR31 REF10 LC10 LC100 LU3M38 manchester
Contextual Info: Data Sheet July 2000 FASTCAT TM LU3X51FT Ethernet Transceiver 10/100Base-TX/FX Features 100 Mbits/s FX Transceiver 10 Mbits/s Transceiver • Compatible with IEEE 802.3u 100Base-FX standard ■ Reuses existing twisted-pair I/O pins for compatible fiber-optic transceiver pseudo-ECL PECL