EP610-30 EQUIVALENT Search Results

EP610

Abstract: EP610-30 altera ep610 EP610-Z5 FLIPFLOP SCHEMATIC 74HC EP610-25 EP610-35 MOPE EP610-40
Contextual Info: HIGH PERFORMANCE 16 MACROCELL EPLD FEATURES CONNECTION DIAGRAM CLKl 3 n I/O Q 10[3 3 i/O □ i/o QT 3 3 3 3 3 3 3 i/o^ I/O J j j I/O Q I/O £9 1/0 0 i/o [ 0 INPUT ^ GNO ^ O EP610 The Altera EP610 Programmable Logic Device is capable of implementing over 600 equivalent gates of

Contextual Info: EP610 EPLDs High-Performance 16-Macrocell Devices Data Sheet September 1991, ver. 2 Features □ □ □ □ □ □ □ □ □ □ General Description A ltera's EP610 Erasable Programmable Logic Devices EPLDs can implement up to 600 equivalent gates of SSI and MSI logic functions in

Contextual Info: EP610 EPLD □ Features □ □ □ □ □ General Description Altera's EP610 Erasable Programmable Logic Device EPLD can implement up to 600 equivalent gates of SSI and MSI logic functions. It is available in space-saving w indowed ceramic or OTP plastic 24-pin, 300-mil DIP and

EP610PC-35

Abstract: ep610di EP610DC-25 EP610DC-30 EP610LI EP610LC30 16 macrocell EP610PC EP610PC-30 EP610-30
Contextual Info: EP610 HIGH-PERFORMANCE 16-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3177, OCTOBER 1988—AUGUST 1989 • High-Density (Over 600 Gates) Replacement for TTL and 74HC DUAL-IN-LINE PACKAGE (TOP V IE W ) • Virtually Zero Standby Power . . . Typ 20 pA

fp6102

Abstract: FP6101 EP610-30 equivalent EP610-30 FP610 EP610 TI EP610 SSI IC adder L-72 EP610-35
Contextual Info: EP610 EPLD J Features J J J J J General Description Programm able clock option for independent clocking of all registers Macrocells in d ivid u ally programmable as D, T, JK , or SR flip-flops, or for combinatorial operation Extensive third-party software and programm ing support

EP610

Abstract: Altera September 1991 EP610-20 acht30
Contextual Info: altera M7E D corp 05^5375 ODDgPbb T lg W ALT EP610 EPLDs High-Performance 16-Macrocell Devices Data Sheet September 1991, ver. 2 □ □ Features □ □ □ □ □ □ □ □ □ General Description H igh-density replacem ent for TTL and 74HC w ith up to 600 gates

P610T

Contextual Info: AN b rVa\ LI IJ LI □ J □ □ □ LI □ H igh-d en sity re placem ent for T T L and 74 H C with up to 600 gates H ig h -p e rfo rm an ce 16-m acrocell E P L D w ith tPD = 15 ns and counter frequencies up to 83 M H z Z ero -p o w e r operation 20 |iA standby

ALTERA EP610

Abstract: MIL-STD-883-compliant
Contextual Info: EP610 MIL-STD-883-Compliant EPLD Features □ □ □ □ □ □ High-performance, 16-macrocell Classic EPLD Combinatorial speeds with tPD = 35 ns Counter frequencies up to 28.5 MHz Pipelined data rates up to 37 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs

FC SUFFIX altera

Contextual Info: Classic EPLD Family Data Sheet M arch 1995, ver. 2 Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ Table 1. Classic Device Features Feature EP22V10 EP22V10E EPB10 EP610T EP610I EP910 EP910T EP910I EP1810 EP1810T Available gates 400 600 600 900 900 1,800 Usable gates

Altera EP1810

Abstract: EP1810 EP600I EP610 EP610-15 EP610-20 EP910 EP610 "pin compatible"
Contextual Info: Classic EPLD Family June 1996, ver. 3 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of up to 900 usable gates see Table 1 Device erasure and reprogramming with advanced, non-volatile EPROM configuration elements

ep600i

Abstract: EP1800I EP610ILI-12 altera ep610 altera EP1810 EP1800 altera ep900i
Contextual Info: Classic EPLD Family June 1996, ver. 3 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of up to 900 usable gates see Table 1 Device erasure and reprogramming with advanced, non-volatile EPROM configuration elements

ep330

Abstract: vhdl code for 4 bit counter vhdl code for sr flipflop EP610 ORDERING EPLD 900
Contextual Info: Classic Programmable Logic Device Family Data Sheet August 1993, ver. 1 □ Features □ □ □ □ □ □ □ □ □ Complete EPLD fam ily with logic densities up to 1,800 available gates 900 usable gates . See Table 1. M ultiple 20-pin PAL and GAL replacem ent and integration

Date Code Formats Altera EPF10K

Abstract: ep22v10 5962-9061102XA 5962-8854901xa 8686401LA 5962-8686401LA lift controller in vhdl ALTERA PART MARKING EPM7160 EPX780 transistor b2020
Contextual Info: Introduction Contents March 1995 Introduction The PLD Advantages of Altera

ALTERA EP1810LC-45

Abstract: EP1810LC-45 EP1810LC-35 EP1810JC-45 EP1810jC-35 EP1810JC EP1810LC45
Contextual Info: EP1810 HIGH-PERFORMANCE 48-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3232. FEBRUARY 1989-R E V IS E D AUGUST 1989 • Erasable, User-Configurable LSI Circuit Capable of Implementing 2100 Equivalent Gates of Conventional and Custom Logic CHIP-CARRIER PACKAGE

EP1810JC-45

Abstract: logicaps schematic capture manual programming manual EP910 Flip flop JK cmos
Contextual Info: EP1810 HIGH-PERFORMANCE 48-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLO D3232, FEB RU ARY 1 9 8 9 -R E V IS E D AU GU ST 1989 • Erasable, User-Configurable LSI Circuit Capable of Implementing 2100 Equivalent Gates of Conventional and Custom Logic

programming manual EPLD EPS448

Abstract: Altera EPM5128 EPM7064-12 leap u1 EP-900910 PLE3-12a tcl tv circuit altera eplds EP610 "pin compatible" ALTERA MAX 5000
Contextual Info: Data Book TENTH ANNIVERSARY A Decade of Leadership A u g u s t 1993 Data Book August 1993 A-DB-0793-01 Altera, MAX, and M A X+PLUS are registered trademarks of Altera Corporation. The following, among others, are trademarks of Altera Corporation: AHDL, M AX+PLUS II, PL-ASAP2, PLDS-HPS, PLS-ADV, PLS-ES, PLS-FLEX8, PLS-FLEX8/H P, PLS-FLEX8/SN , PLS-HPS, PLS-STD, PLS-W S/H P,

Contextual Info: intel MILITARY ¡PLD610 16-MACROCELL CHMOS juPLD Function, Pin, and JEDEC Compatible with 5C060, EP600, EP610, EP630 and CE630 PLDs Programmable Clock System with 2 Synchronous Clocks and Asynchro­ nous Clocking Option on all Registers tpD 15 ns, 66 MHz Counter Frequency

npld610

Abstract: NPLD610-10 PALCE610 EP610 ORDERING PLD610 DPLD610-25 intel 85C060 85C060 TNPLD610 intel PLD
Contextual Info: in tj ¡PLD610 FAST 16-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610,85C060 and 5C060 PLDa • * m - m r ' "< ^ . *. » • tpQ 10 ns, 100 MHz Counter Frequency w/lnternal Feedback ■ Ice = 105 m A max-@ 1 MHz

85c060

Abstract: intel iPLD610 pld610 P85C060-25 D85C060-15 EP610 ORDERING intel 85C060 intel PLD 29045 EP610 "pin compatible"
Contextual Info: in tJ . ¡PLD610/85C060 FAST 16-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610,85C060 and 5C060 PLDs • tPD 10 ns, 100 MHz C ounter Frequency w /ln tern al Feedback ■ Extensive Softw are and Programming

DPLD610-15

Abstract: PLD610-10 PLD610 DPLD610-25 EP610 ORDERING intel 85C060 intel PLD TNPLD610 2164 intel 85C060
Contextual Info: in tj ¡PLD610 FAST 16-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610,85C060 and 5C060 PLDs • tpo 10 ns, 100 MHz Counter Frequency w/lnternal Feedback ■ Icc = 1 0 5 mA max. @ 1 MHz ■ Programmable Low-Power Option for

d6105

Contextual Info: PLD610 PRELIMINARY OYPRESS SEMICONDUCTOR • Function, pin, and JEDEC compatible with EP600, EP610, EP630,85C060, and PALCE610 PLDs • Veiy high performance — tpo = 10 ns • 16 I/O macrocells, each having: — Choice of combinatorial or regis­ tered output

Contextual Info: Ml intpl 6 1992 ÌPLD610 FAST 16-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610,85C060 and 5C060 PLDs • tpo 10 ns, 100 MHz Counter Frequency w/lnternal Feedback ■ Extensive Software and Programming Support via Intel and Third Party Tools

P85C060-25

Abstract: D85C060 PLD610-25 D85C060-25 intel 85C060 D85C060-15 IPLD610-15 EP610 ORDERING p85c060 N85C060-12
Contextual Info: INTEL CORP tIEMORY/PLD/ in t e l SbE D • HfiSblTb D077infl fl3£ ^p ÌPLD610/85C060 FAST 16-MACROCELL CMOS PLD h ITL2 ^ '^ - o 0 Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610,85C060 and 5C060 PLDs ■ tpo 10 ns, 100 MHz Counter Frequency

shiftregisters

Abstract: EP910 altera TTL library 74LS series logic gates 74LS EP1810 EP1810-45 EP610 PLE40 altera logicaps TTL library
Contextual Info: EP1810 Y 7 \ m HIGH PERFORMANCE 4 8 MACROCELL EPLD m 10 I U FEATURES GENERAL DESCRIPTION • Erasable, User-Configurable LSI circuit capable of implementing 2100 equivalent gates of conven­ tional and custom logic. • Speed equivalent to 74LS TTL with 33 MHz clock