FORE ATM CRC Search Results

fore systems forerunner

Abstract: forerunner atm intel i960 RISC intel 486 dx processor Intel 486 DX apple macintosh 486 DX
Contextual Info: ATM ATM FORE SYSTEMS ForeRunner Family of ATM Adapters For PC/Macintosh and Servers Adapters For EISA, Nubus, and PCI Bus • Windows NT, Novell Netware, Mactcp And Appletalk Support ■ Multimode Fiber and Category 5 UTP ■ Flexible Cell Processing Software

AAL5 SAR

Abstract: VMA-200 indigo intel i960 RISC forerunner atm VME64 GIA-200 irix
Contextual Info: ATM FORE SYSTEMS ForeRunner Family of ATM Adapters For UNIX Systems Adapters For EISA, PCI, SBUS, MCA, GIO and VME Bus Architectures • Multimode Fiber and Category 5 UTP ■ Flexible Cell Processing Software Can be Upgraded to Support Evolving ATM and Rate Control

PCA Board

Abstract: 486 processor types fore systems forerunner
Contextual Info: ATM FORE SYSTEMS ForeRunner PCA-200PC PCI Bus ATM Adapter TECHNICAL SPECIFICATIONS Operating Systems • Windows NT 3.5 or 3.51 ■ Novell Netware 3.12 or 4.x Servers Only Machine Types ■ Any Fully-Compliant Peripheral Component Interconnect (PCI) Bus

EISA Bus

Abstract: forerunner atm crc 10 in atm Scatter-Gather 486 processor types
Contextual Info: ATM FORE SYSTEMS ForeRunner ESA-200EPC EISA Bus ATM Adapter TECHNICAL SPECIFICATIONS Operating Systems • Windows NT 3.5 or 3.51 ■ Novell Netware 3.12 or 4.x Servers Only PC Types ■ Any Fully-Compliant Extended Industry Standard Architecture (EISA) Specification PC or Server

Contextual Info: t f .a n S w it c h Technical Manual for Service Interface S A R A -L ite - X -TABLE OF CONTENTS S E C T IO N PAGE 1.0 O ve rvie w .4

ups SERVICE MANUAL

Abstract: CRC32 CRC-32 TXC-05551 TXC-05551-TM1
Contextual Info: t r a n S w it c h • Technical Manual for Service Interface S A R A -L ite - TABLE OF CONTENTS SECTION PAGE 1.0 Overview .4

Contextual Info: ÌS '— A 1/1 JT2F Device / 1 Tim H 6 Mbit/s JT2 Framer TXC-03702B - DATA SHEET FEATURES DESCRIPTION • Framer for: - ITU Recommendation G.704 - NTT-specified 6312 kbit/s format - NTT-specified technical reference of cell relay interface The JT2 Framer JT2F is a CMOS VLSI device that

GG1Q

Contextual Info: 1.0 Product Description 1.1 Introduction Figure 1-1 is a detailed block diagram o f the Bt8222. For transmission from the host system, octet-wide data is input from the UTOPIA or FIFO ports. The host data is assembled into ATM cells and then formatted for serial line transmission

ssy 1920

Abstract: L8222
Contextual Info: llOii 1.0 Product Description - The Bt8222 ATM Physical Interface PHY) device is a receiver/transmitter which converts several types of frames to ATM cells and vice versa. The device contains framers for DS3, E3, E4, STS-1, STS-3c nd STM-1. This chapter provides an

Rockwell 6551

Contextual Info: Preliminary Information This document contains information on a product under development. The parametric information contains target parameters that are subject to change. RS8235 Endstation ATM ServiceSAR With xBR Traffic Management The RS8235 Service Segm entation and Reassembly C ontroller

BIP 109

Contextual Info: TOSHIBA Quad Physical Layer Controller 1 9 9 7 T C 3 5 8 2 3 F P R E L I M I N A R Y R E V I S I O N D A T A TOSHIBA AMERICA ELECTRONIC COMPONENTS, I NC 0. 4 B O O K 199 7 Toshiba Am erica Electronic Com ponents, Inc. Published in O ctober, 199 7 T o s h ib a p ro d u c ts d e s c rib e d in th is d o c u m e n t a re n o t a u th o riz e d fo r use as c ritic a l c o m p o n e n ts in life s u p p o rt s y s te m s w ith o u t th e w ritte n c o n s e n t o f th e a p p ro p ria te o ffic e r o f T o s h ib a

74222 fifo

Abstract: NAIS 210 GR-499-CORE XRT7295 XRT7296 XRT7300 S/74222 fifo
Contextual Info: áç XRT7245 PRELIMINARY DS3 UNI FOR ATM DECEMBER 1999 REV. 1.03 GENERAL DESCRIPTION • Contains on-chip 16 cell FIFO configurable in The XRT7245 DS3 ATM User Network Interface (UNI device is designed to provide the ATM Physical Layer (Physical Medium Dependent and Transmission Convergence sub-layers) interface for the public

auto tran 600

Contextual Info: t h a n S w it c h „ CUBIT Device CellBus Bus Switch TXC-05801 X- DATA SHEET FEATURES DESCRIPTION • UTOPIA or ALI-25 physical-layer cell Interface CUBIT Is a single-chip solution for Implementing low-cost ATM multiplexing and switching systems,

ic 339

Abstract: rele nais dmo 465 XRT74L74 XRT74L74IB MIPS 32-bit bus architecture F25 marking DMO 465 R
Contextual Info: XRT74L74 PRELIMINARY 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER OCTOBER 2003 REV. P1.1.1 GENERAL DESCRIPTION The XRT74L74 4 Channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller is designed to support ATM direct mapping and

Contextual Info: |p I 1.0 Product Description The Bt8230 Segmentation and Reassembly Controller SRC incorporates a host interface, Asynchronous Transfer Mode (ATM) Adaptation Layer processing, and line interfaces in a single device. This highly integrated ATM device combines

8052 microcontroller Intel

Abstract: GR-499-CORE XRT7295 XRT7296 XR-T7296 XRT7300 flowchart of LCD interface with 8051 fc22825
Contextual Info: áç XRT7245 PRELIMINARY DS3 UNI FOR ATM DECEMBER 1999 REV. 1.03 GENERAL DESCRIPTION • Contains on-chip 16 cell FIFO configurable in The XRT7245 DS3 ATM User Network Interface (UNI device is designed to provide the ATM Physical Layer (Physical Medium Dependent and Transmission Convergence sub-layers) interface for the public

dmo 265 r

Abstract: dmo 365 r MPC860 jtag AC16 GR-499-CORE I960 MPC860 XRT73L03 XRT74L73 XRT74L73IB
Contextual Info: XRT74L73 PRELIMINARY 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER OCTOBER 2003 REV. P1.0.1 GENERAL DESCRIPTION The XRT74L73 3 Channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller is designed to support ATM direct mapping and

HITACHI WORKBENCH 1.01

Abstract: ALP 102 B4 i386ex i386ex intel i386 TTC 103 435 AC16 AD17 ALPS 328 TC55V1325FF-7
Contextual Info: ICs for Communications ATM Layer Processor ALP PXB 4350 E Version 1.1 Preliminary Data Sheet 09.98 DS 2 PXB 4350 E Revision History: Current Version: 09.98 Previous Version: Preliminary Data Sheet 08.97 DS 1 Page Page (in previous (in current Version) Version)

Contextual Info: SIEMENS ICs for Communications ATM Layer Processor ALP PXB 4350 E Version 1.1 Preliminary Data Sheet 09.98 DS 2 PXB 4350 E Revision History: Current Version: 09.98 Previous Version: Preliminary Data Sheet 08.97 DS 1 Page (in previous Version) Page (in current

L8233A

Contextual Info: J0}i\ 1.0 Bt8233 Product Overview - 1.1 Introduction The Bt8233 Service Segmentation and Reassembly Controller ServiceSAR delivers a wide range of advanced Asynchronous Transfer Mode (ATM), ATM

ALi m 3329

Contextual Info: 1 ABR SAR Overview The IDT77252 ABR SAR PCI ATM Controller is a member of IDT's family of products for Asynchronous Transfer Mode ATM networks. The ABR SAR performs both the ATM Adaptation Layer (AAL) Segmentation and Reassembly (SAR) function and the ATM layer

L8222

Abstract: OQ 051
Contextual Info: 1.0 Product Description 1.1 Introduction Figure 1-1 is a detailed block diagram of the Bt8222. For transmission from the host system, octet-wide data is input from the UTOPIA or FIFO ports. The host data is assembled into ATM cells and then formatted for serial line transmission

Contextual Info: 1.0 RS8234 Product Overview 1.1 Introduction The RS8234 Service Segmentation and Reassembly Controller Sem'ceSAR delivers a wide range of advanced ATM, AAL, and service-specific features in a highly integrated CMOS package. Some of the RS8234 service-level features provide system designers with

CL9100

Abstract: 27mhz remote control receiver ic rx 2b circuit FO AVIA-GTX k1525a AVIA GTX CL9110 aviadmx avia avia-dmx Avia-500
Contextual Info: BACK AViA-DMX MPEG-2 Transport Demultiplexer AViA-GTX Graphics Transport I/O User’s Manual 92-9210-301 C-Cube Microsystems This document is preliminary and is still undergoing technical review. While the information is believed to be accurate, it may contain errors.