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    FPGA 144 CPGA ASIC Search Results

    FPGA 144 CPGA ASIC Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TE512S32-25LC Rochester Electronics LLC TE512S32 - Field Programmable Gate Array, CMOS, PQFP128 Visit Rochester Electronics LLC Buy
    TE505S16-40QC-G Rochester Electronics LLC TE505S16 - Field Programmable Gate Array, CMOS, PQFP208 Visit Rochester Electronics LLC Buy
    TE505S16-40QI Rochester Electronics LLC TE505S16 - Field Programmable Gate Array, CMOS, PQFP208 Visit Rochester Electronics LLC Buy
    TE505S16-25QC-G Rochester Electronics LLC TE512S32 - Field Programmable Gate Array, CMOS Visit Rochester Electronics LLC Buy
    TE512S32-40LC Rochester Electronics LLC TE512S32 - Field Programmable Gate Array, CMOS, PQFP128 Visit Rochester Electronics LLC Buy

    FPGA 144 CPGA ASIC Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    verilog code for histogram

    Abstract: verilog hdl code for multiplexer 4 to 1 FPGA 144 CPGA 172 PLCC ASIC cmos logic 4000 series 5-input-XOR verilog code for pci to pci bridge verilog code for johnson counter vhdl code for multiplexer 16 to 1 using 4 to 1 3 to 8 line decoder vhdl IEEE format QL2003
    Text: QuickLogic Corporation provides very-high-speed programmable ASIC solutions for designers of high-performance systems who must get their products to market quickly. The company was founded by the engineers who invented the PAL device and PALASM software. Through fast time-to-market, low development


    Original     		PDF RS-232 verilog code for histogram verilog hdl code for multiplexer 4 to 1 FPGA 144 CPGA 172 PLCC ASIC cmos logic 4000 series 5-input-XOR verilog code for pci to pci bridge verilog code for johnson counter vhdl code for multiplexer 16 to 1 using 4 to 1 3 to 8 line decoder vhdl IEEE format QL2003

    16X24B

    Abstract: CF160 PF100 PF144 PL84 CPGA Package Diagram
    Text: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …4,000 usable ASIC gates, 122 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    Original     		PDF QL16x24B 16-by-24 84-pin 100-pin 144-pin 160-pin 16-bit 16x24B CF160 PF100 PF144 PL84 CPGA Package Diagram

    QL3012

    Abstract: QL3025 QL3040 QL3060 QL4016 QL4090 footprint pqfp 208 QuickLogic Military FPGA Introduction
    Text: QuickLogic Military FPGA Introduction Military FPGA Combining High Performance and High Density Military FPGA Introduction DEVICE HIGHLIGHTS Device Highlights Military FPGA • Mil Std 883 and Mil Temp Ceramic ■ Mil Temp Plastic Guaranteed -55 to +125oC


    Original     		PDF 125oC 152-bit 16-bit -55oC, QL3012 QL3025 QL3040 QL3060 QL4016 QL4090 footprint pqfp 208 QuickLogic Military FPGA Introduction

    ttl logic gates

    Abstract: pASIC 1 Family ttl and gate
    Text: pASIC 1 Family ViaLink Technology Very-High-Speed CMOS FPGAs FAMILY HIGHLIGHTS Very High Speed – ViaLink metal-to-metal, programmable-via antifuse technology ensures useful internal logic function speeds at over 100 MHz, and logic cell delays of under 2 ns.


    Original     		PDF 14-input MIL-STD-883D, ttl logic gates pASIC 1 Family ttl and gate

    CPGA routing

    Abstract: No abstract text available
    Text: pASIC 1 Family ViaLink Technology Very-High-Speed CMOS FPGAs FAMILY HIGHLIGHTS Very High Speed – ViaLink metal-to-metal, programmable-via antifuse technology ensures useful internal logic function speeds at over 100 MHz, and logic cell delays of under 2 ns.


    Original     		PDF 14-input QL8x12B MIL-STD-883D, CPGA routing

    QuickLogic ql16x24b-1pl84c

    Abstract: QL16X24B PF144 cmos io QL16X24BH TQFP 144 PACKAGE CF160 PF100 PL84
    Text: QL16x24B/QL16x24BH Wild Cat 4000 Very-High-Speed 4K 12K Gate CMOS FPGA Rev B .4000 usable gates, 122 I/O pins Very High Speed – ViaLinkTM metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    Original     		PDF QL16x24B/QL16x24BH 16-by-24 84pin 100-pin 144-pin 160pin 16-bit QL16x24BH QuickLogic ql16x24b-1pl84c QL16X24B PF144 cmos io TQFP 144 PACKAGE CF160 PF100 PL84

    Mil-Std-883B

    Abstract: smd FFs antifuse programming technology resistance array smd transistor military datasheet CF100 CF160 antifuse QuickLogic
    Text: pASIC Military FPGAs Non-Volatile, High Reliability and High Security Programmable Logic Solutions Rev. A FAMILY HIGHLIGHTS High Reliability -Available in Military Temperature and MIL-STD-883B/SMD -Standard Microcircuit Drawings SMD available Design Security


    Original     		PDF MIL-STD-883B/SMD QL12x16B QL16x24B MIL-STD-883B smd FFs antifuse programming technology resistance array smd transistor military datasheet CF100 CF160 antifuse QuickLogic

    CF100

    Abstract: Mil-Std-883B antifuse programming technology pASIC 1 Family smd FFs CF160
    Text: pASIC Military FPGAs Non-Volatile, High Reliability and High Security Programmable Logic Solutions Rev. A FAMILY HIGHLIGHTS High Reliability -Available in Military Temperature and MIL-STD-883B/SMD -Standard Microcircuit Drawings SMD available Design Security


    Original     		PDF MIL-STD-883B/SMD QL12x16B MIL-STD-883B CF100 antifuse programming technology pASIC 1 Family smd FFs CF160

    QL4090

    Abstract: pASIC 1 Family 160CQFP 208-CQFP
    Text: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …4,000 usable ASIC gates, 122 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    Original     		PDF QL16x24B 16-by-24 84-pin 100-pin 144-pin 160-pin 16-bit V144-TQFP QL24x32B QL4090 pASIC 1 Family 160CQFP 208-CQFP

    5-input-XOR

    Abstract: verilog code for correlate verilog code for pci express schematic XOR Gates pASIC 1 Family 3-input-XOR FPGA 144 CPGA 172 PLCC ASIC antifuse programming technology TRANSISTOR D 1978 verilog code for pci
    Text: 7-31 Leading The Revolution in FPGAs 7-32 1993 1994 1995 1996 1997 1998 1999 2000 SPLD CPLD* FPGA • * = CPLD numbers include FLEX 8000 Source: Pace Technologies, Feb ‘96 PLD Market will see a 25% compound growth, reaching $6.7B in the year 2000, ■ FPGAs will see a compound growth rate of 27%, reaching $3.0B by the year 2000


    Original     		PDF

    68-PIN

    Abstract: 84-PIN cpga pinout 208-pin cpga
    Text: Military 5.0V pASIC 1 Family Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA Military 5.0V pASIC 1 Family DEVICE HIGHLIGHTS FEATURES Device Highlights Features Very High Speed • ViaLink“ metal-to-metal programmable technology, allows counter speeds over 150 MHz and


    Original     		PDF 24x32B CF208 M/883C 8x12B 12x16B 16x24B 24x32B 68-pin 84-pin CG144 cpga pinout 208-pin cpga

    208-pin cpga

    Abstract: No abstract text available
    Text: Military 5.0V pASIC 1 Family Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA last updated 5/15/2000 Military 5.0V pASIC 1 Family DEVICE HIGHLIGHTS FEATURES Device Highlights Features Very High Speed • ViaLink“ metal-to-metal programmable technology, allows counter speeds over 150 MHz and


    Original     		PDF 24-by-32 208-pin 24x32B CF208 M/883C 8x12B 12x16B 16x24B 208-pin cpga

    ESBGA

    Abstract: Star Sea Electronics OA21 micro power intellect 391-Pin Electromec Zycad
    Text: GF250F ProASIC Product Family Highest Performance, Highest Density, Programmable CMOS ASICs The GF250F™ ProASIC™ product family is the highest performance and highest gate count programmable ASICs released in the GateField™ portfolio. The GF250F family offers reprogrammable ASIC solutions to applications in the consumer, computer and communications markets.


    Original     		PDF GF250F GF250FTM GF200F GF200F, GF250F, ESBGA Star Sea Electronics OA21 micro power intellect 391-Pin Electromec Zycad

    amd 29050

    Abstract: VHDL CODE FOR PID CONTROLLERS 20630 Xilinx XC2000 LCC100 UD09 LCC84 UD10 8251 uart vhdl MCT8
    Text: Digital Integration Introduction When integrating the digital part of modern electronic systems, various technical and financial criteria must be considered. Over 10 years of ASIC experience have shown that no one methodology can meet all requirements at the same time.


    Original     		PDF 10-May-96 amd 29050 VHDL CODE FOR PID CONTROLLERS 20630 Xilinx XC2000 LCC100 UD09 LCC84 UD10 8251 uart vhdl MCT8

    MQFPL160

    Abstract: UD02 UD09 LCC100 QuickLogic Military FPGA Introduction UD10 atmel 336 20RA10 XC7000 PGA68
    Text: Digital Integration Design done by Customer and TEMIC MATRA MHS Digital Integration Introduction When integrating the digital part of modern electronic system, various technical and financial criteria are considered. Over 10 years of ASIC experience have shown


    Original     		PDF

    Untitled

    Abstract: No abstract text available
    Text: n Military Logic CeN Arrays XC2018B, XC3020B, XC3042B, XC3090B Product Specifications INTRODUCTION Xilinx introduced the first field programmable gate array FPGA in 1985. The development of the PGA was the result of a number of technical breakthroughs and truly


    OCR Scan     		PDF XC2018B, XC3020B, XC3042B, XC3090B

    CPGA

    Abstract: 144 CERAMIC PIN GRID ARRAY CPGA Xilinx XC3090 FPGA 144 CPGA ASIC standard military device CPGA132 MO-082
    Text: K Military Logic Cell Arrays XC2018B, XC3020B, XC3042B, XC3090B Product Specifications INTRODUCTION Device Xilinx introduced the first field programmable gate array FPGA in 1985. The development of the PGA was the result of a number of technical breakthroughs and truly


    OCR Scan     		PDF XC2018B, XC3020B, XC3042B, XC3090B MIL-STD-883 2010/B 1010/C 2001/E CPGA 144 CERAMIC PIN GRID ARRAY CPGA Xilinx XC3090 FPGA 144 CPGA ASIC standard military device CPGA132 MO-082

    Untitled

    Abstract: No abstract text available
    Text: Q L16X24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS .4,000 usable ASIC gates, 122 I/O pins Very High Speed - ViaLink metal-to-metal program m able-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    OCR Scan     		PDF L16X24B 16-by-24 84-pin 100-pin 144-pin 160-pin 16-bit 16x24B PF144C

    ttl and gate

    Abstract: No abstract text available
    Text: pASIC 1 Family ViaLink Technology Very-High-Speed CMOS FPGAs FAMILY HIGHLIGHTS Q Very High Speed - ViaLink metal-to-metal, programmable-via antifuse technology ensures useful internal logic function speeds at over 100 MHz, and logic cell delays of under 2 ns.


    OCR Scan     		PDF 14-input MIL-STD-883D, ttl and gate

    PL84C

    Abstract: CPGA Package Diagram TQFP 10 10
    Text: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS .4,000 usable ASIC gates, 122 I/O pins Very High Speed - ViaLink" metal-to-metal programmable-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    OCR Scan     		PDF QL16x24B 16-by-24 84-pin 100-pin 144-pin 160-pin 16-bit 16x24B PF144C PL84C CPGA Package Diagram TQFP 10 10

    16X24

    Abstract: No abstract text available
    Text: QL16x24B/QL16x24BH WildCat 4000 Very-High-Speed 4K 12K Gate CMOS FPGA Rev B pASIC HIGHLIGHTS B Very High Speed - V iaL ink metal-to-metal program m able-via anti­ fuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    OCR Scan     		PDF QL16x24B/QL16x24BH 16-by-24 84pin 100-pin 144-pin 160pin 16-bit QL16x24BH 16X24

    Untitled

    Abstract: No abstract text available
    Text: QL16x24B Wildcat 4000 Very-High-Speed 4K 12K Gate CMOS FPGA Rev A pASIC HIGHLIGHTS Very High Speed - ViaLink metal-to-metal programmable-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. B High Usable Density - A 16-by-24 array of384 logic cells provides 12,000


    OCR Scan     		PDF QL16x24B 16-by-24 of384 84pin 100-pin 144-pin 160pin 16-bit

    FPGA 144 CPGA 172 PLCC ASIC

    Abstract: A144 CY7C386A CY7C387A CY7C387A-2GC CY7C388A CY7C387A2AI
    Text: CY7C387A CY7C388A PRELIMINARY CYPRESS Very High Speed 8K 24K Gate CMOS FPGA Features — 16-bit counter operating at 100 MHz consumes 50 mA — Minimum I o l of 12 mA and Ioh °f • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies


    OCR Scan     		PDF CY7C387A CY7C388A 145-pin 245-pin 144-pin 208-pin 160-pin 225-pin 16-bit FPGA 144 CPGA 172 PLCC ASIC A144 CY7C386A CY7C387A-2GC CY7C388A CY7C387A2AI

    QuickLogic ql16x24b-1pl84c

    Abstract: No abstract text available
    Text: QL16X24B WildCat 4000 Very-High-Speed 4K 12K Gate CMOS FPGA pASIC HIGHLIGHTS B Very High Speed - ViaLink metal-to-metal programmable-via anti­ fuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. H High Usable Density - A 16-by-24 array of 384 logic cells provides


    OCR Scan     		PDF QL16X24B 16-by-24 84-pin 144-pin 169-pin 16-bit QL16x24B 16x24B QuickLogic ql16x24b-1pl84c