GA1210E Search Results

Contextual Info: S E M I C O N D U C T O P I N C 7QS1 :0 M P U T ING AND NETWORKING Figure 1. Block Diagram VOO T1 CLKIN GA1210E FBIN EN2 INV1 Data Sheets Clock Doubter/ Two-Phase Generator Features • 2X clock multiple generator TriQuint’s GA1210E is a low -skew TTL-level clock doubler chip. It produces m ultiple clock

Contextual Info: VCC T1 C L K IN F B IN EN2 IN V 1 TO GA1210E GND Low-Skew 771 Clock Doubler/ Two-Phase Clock Generator GND QO Q1 02 Q3 TriQuint’s GA1210E is a low-skew TTLlevel clock doubler chip. It produces m ultiple clock outputs, at precisely 2X the input frequency, which are all phasealigned to a periodic clock input signal. The

Contextual Info: T R I Q U I N T S E M I C O N D U C T O R , I N C 7Q£t GA1210E Figure 1. Block Diagram VD D T1 CLKIN FBIN EN2 INV1 TO GND Clock Doubler / Two-Phase Generator Features • 2X clock multiple generator • Two-phase clock generator T riQ u in t’s G A 1 2 1 OE Is a lo w -s k e w T T L -le v e l c lo c k d o u b le r c h ip . It p ro d u c e s

gazelle microcircuits

Contextual Info: NOM 2 i 1990 GA1210E Low-Skew TTL Clock Doubler Two-Phase Clock G enerator gazelle General Description Features Gazelle’s GA121OE is a low-skew TTL-level clock doubler chip. It produces multiple clock outputs, at precisely 2X the input frequency, which are all phase-aligned to a periodic clock input signal. The

Contextual Info: G A Z E LL E M I C R O C I R C U I T S INC S'ÎE ]> • 3fl3bOB5 OOOOO'îl ô W Ê G k l T^i-OD r m Q A 121OE Low-Skew TTL Clock Doubler Two-Phase Clock Generator J è gazelle General Description Features Gazelle's GA1210E is a low-skew TTL-level clock doubler chip. It

fbii

Abstract: motherboard ga clock generator for 4040
Contextual Info: COMPUTING AND^NET WORKING Figure 1. Block Diagram VDO T1 CLKIN GA1210E FBIN EN2 INVI TO GND Clock Doubler/ Two-Phase Generator Features TriQuint's GA1210E is a low-skew TTL-level clock doubler chip. It produces multiple clock outputs, at precisely 2X the input frequency, which are all phase-aligned to a periodic clock

013Q3

Contextual Info: S COMPUTING AND E M I C O N D U T1 T 0 R , I N C . NETWORKING Figure 1. Block Diagram VDD C CLKIN GA1210E FBIN EN2 IN V I TO GND Data Sheets Clock Doubler/ Two-Phase Generator Features • 2 X clock multiple generator TriQuint's GA1210E is a low-skew TTL-level clock doubler chip. It produces multiple clock

MQUAD

Contextual Info: T R I Q U I N T S E M I C O N D U C T O R, I N C . GA1210E Figure 1. Block Diagram VDD T1 CLKIN FBIN EN2 INV1 T0 GND 8 7 6 5 4 3 2 1 PHASE-LOCKED LOOP PLL Clock Doubler / Two-Phase Generator CONTROL LOGIC MUX DIVIDE LOGIC GND OUTPUT BUFFER OUTPUT BUFFER

Contextual Info: r B t § tt / üf r S E M I C O N D U C T O R , I N C IQ # C O M P U T I N G AND NETWORKING Figure 1. Block Diagram CLKIN GA1210E FBIN Clock Doubler/ Two-Phase Generator Features TriQuint's GA1210E is a low-skew TTL-level clock doubler chip. It produces multiple clock

Contextual Info: • K5.' C O M P U T I N G VCC T1 A N D N E T W O R K I N G C LK IN F B IN EN 2 IN V I TO GA1210E GND Low-Skew 771 Clock Doubler/ Two-Phase Clock Generator Features TriQuint’s GA1210E is a low-skew TTLlevel clock doubler chip. It produces m ultiple clock outputs, at precisely 2X the

Contextual Info: Figure 1. Block Diagram F l F l F I F I F ] □ _ Clock Doubler/ Ttoo-Phase Generator PHASE-LOCKED CONTROL LOGIC LOOP P IL \ MUX DIVIDE "0 OUTPUT BUFFER OUTPUT BUFFER OUTPUT BUFFER LlJ Li] /— Oata Sheets F l GA1210E LOGIC OUTPUT BUFFER lD OUTPUT BUFFER

SC1110

Contextual Info: PRELIMINARY DEVICE SPECIFICATION LOW-SKEW TTL CLOCK DOUBLER/TWO-PHASE CLOCK GENERATOR SC1210 FEATURES GENERAL DESCRIPTION • Pin-for-pin replacement for Triquint/Gazelle GA1210E AMCC’s SC1210 is a low-skew TTL-level clock doubler chip providing high-speed clock generation and routing.

Contextual Info: T R I Q U I re m COMPUTING AND N T S E M I C O N D U C T O R , / NETWORKING Figure 1. Block Diagram VD D TI I N C CLKIN GA1210E FBIN EN2 INVI TO GND Data Sheets Clock Doubler/ Two-Phase Generator Features • 2X clock multiple generator TriQuint's GA1210E is a low-skew TTL-level clock doubler chip. It produces multiple clock

Contextual Info: Il I U U S E M I C O N D U C T O R , I N C I T O S I GA1210E Figure 1. Block Diagram Clock Doubler / Two-Phase Generator F e a tu re s • 2X clock multiple generator • Two-phase clock generator TriQuint’s GA121OE is a low-skew TTL-level clock doubler chip. It produces

Contextual Info: Integrated Circuit Systems, Inc. AV9172 Low Skew Output Buffer General Description Features The AV9172 is designed to generate low skew clocks for clock distribution in high-performance PCs and workstations. It uses phase-locked loop technology to align the phase and

Contextual Info: T R I Q U I N T S E M I C O N D U C T O R , I N C 7QS1 G A 1 1 1 0 E Figure 1. Block Diagram VDD CLKIN FBIN SO TO GND Multi-Phase Clock Buffer Features • Zero-propagation-delay clock buffer » Output skew controlled to ±250 ps typ. , ± 500 ps (max.) TriQuint’s GA1110E is a low-skew TTL-level clock buffer chip with multi­

AV9172-07

Abstract: marking 2x AV9172 AV9172-01 AV9172-03 GA1210
Contextual Info: Integrated Circuit Systems, Inc. AV9172 Low Skew Output Buffer General Description Features The AV9172 is designed to generate low skew clocks for clock distribution in high-performance PCs and workstations. It uses phase-locked loop technology to align the phase and

Contextual Info: AV9172 Integrated Circuit Systems, Inc. Advance Information Low Skew Output Buffer General Description Features The AV9172 is designed to generate low skew clocks for clock distribution in high-performance PCs and workstations. It uses phase-locked loop technology to align the phase and frequency

Contextual Info: I N I Q U I C O M P U T I N G AND -V ' S E M I C 0 N D U T1 T O F , I N C N E T W O R K I N G GA1110E Figure 1. Block Diagram VDD C C LK IN F B IN S1 SO TO GND Data Sheets Multi-Phase Clock Buffer Features • Zero-propagation-delay clock buffer TriQuint's GA1110E is a low -skew TTL-level clock buffer chip w ith m ulti-phase clock

marking 2x

Abstract: AV9172 AV9172-01 AV9172-03 AV9172-07 D-35
Contextual Info: AV9172 Integrated Circuit Systems, Inc. Low Skew Output Buffer General Description Features The AV9172 is designed to generate low skew clocks for clock distribution in high-performance PCs and workstations. It uses phase-locked loop technology to align the phase and frequency

Contextual Info: T R I Q U I N T S E M I C O N D U C T O R , I N C 7Q £ t GA1110E Figure 1. Block Diagram VDD T1 CLKIN FBIN S1 SO TO GND Multi-Phase Clock Buffer Features • Zero-propagation-delay clock buffer • Output skew controlled to ±250 ps typ. , ± 500 ps (max.)

Contextual Info: AV9172 Integrated Circuit Systems, Inc. Advance Information Low Skew Output Buffer General Description Features The AV9172 is designed to generate low skew clocks for clock distribution in high-performance PCs and workstations. It uses phase-locked loop technology to align the phase and frequency

GAL11

Abstract: motherboard ga
Contextual Info: T R I Q U I N T S E M I C O N D U C T O R , I N C TOSI GA1110E Figure 1. Block Diagram VDD CLKIN FBIN TO GND Multi-Phase Clock Buffer Features • Zero-propagation-delay clock buffer • Output skew controlled to ±250 ps typ. , ± 500 ps (max.) TriQuint’s GA1110E is a low-skew TTL-level clock buffer chip with m ulti­

Contextual Info: T R I Q COMPUTING AND U I N T S E M I C O N D U T1 T 0 R , I N C NETWORKING GA1110E Figure 1. Block Diagram VDD C CLKIN FBIN S1 SO TO GND Data Sheets Multi-Phase Clock Buffer Features TriQuint’s GA1110E is a low-skew TTL-level clock buffer chip with multi-phase clock