GA1110E Search Results

Contextual Info: T R I Q U I N T S E M I C O N D U C T O R , I N C 7QS1 G A 1 1 1 0 E Figure 1. Block Diagram VDD CLKIN FBIN SO TO GND Multi-Phase Clock Buffer Features • Zero-propagation-delay clock buffer » Output skew controlled to ±250 ps typ. , ± 500 ps (max.) TriQuint’s GA1110E is a low-skew TTL-level clock buffer chip with multi­

Contextual Info: I N I Q U I C O M P U T I N G AND -V ' S E M I C 0 N D U T1 T O F , I N C N E T W O R K I N G GA1110E Figure 1. Block Diagram VDD C C LK IN F B IN S1 SO TO GND Data Sheets Multi-Phase Clock Buffer Features • Zero-propagation-delay clock buffer TriQuint's GA1110E is a low -skew TTL-level clock buffer chip w ith m ulti-phase clock

Contextual Info: '.fit PRELIMINARY DEVICE SPECIFICATION MULTI-PHASE CLOCK GENERATOR/LOW-SKEW TTL CLOCK BUFFER SC1110 I FEATURES GENERAL DESCRIPTION • Pin-for-pin replacement for Triquint/Gazelle GA1110E • “Zero-propagation delay” clock buffer provides ±250 ps typ , ±1 ns (max) input to output delay

Contextual Info: T R I Q U I N T S E M I C O N D U C T O R , I N C 7Q £ t GA1110E Figure 1. Block Diagram VDD T1 CLKIN FBIN S1 SO TO GND Multi-Phase Clock Buffer Features • Zero-propagation-delay clock buffer • Output skew controlled to ±250 ps typ. , ± 500 ps (max.)

GAL11

Abstract: motherboard ga
Contextual Info: T R I Q U I N T S E M I C O N D U C T O R , I N C TOSI GA1110E Figure 1. Block Diagram VDD CLKIN FBIN TO GND Multi-Phase Clock Buffer Features • Zero-propagation-delay clock buffer • Output skew controlled to ±250 ps typ. , ± 500 ps (max.) TriQuint’s GA1110E is a low-skew TTL-level clock buffer chip with m ulti­

Contextual Info: T R I Q COMPUTING AND U I N T S E M I C O N D U T1 T 0 R , I N C NETWORKING GA1110E Figure 1. Block Diagram VDD C CLKIN FBIN S1 SO TO GND Data Sheets Multi-Phase Clock Buffer Features TriQuint’s GA1110E is a low-skew TTL-level clock buffer chip with multi-phase clock

Contextual Info: C T 0 R , I N C C O M PU T IN G AND NETWORKING Figure 1. Block Diagram VDD T1 C LKIN GA1110E FBIN S1 SO TO GND Multi-Phase Clock Buffer Features TriQuint's GA1110E is a low-skew TTL-level clock buffer chip with multi-phase clock generation. It produces multiple clock outputs which are normally phase- and frequencysynchronized to a periodic clock input signal. It offers the user the additional flexibility to

Contextual Info: C i [ 1 P ! 1 I I [J Ci VCC T1 AND N E T W O R K IN G CLKIN FBIN S1 SO TO GND GA1110E Multi-Phase Clock Generator/ Low-Skew TTL Clock Buffer Features TriQuint’s GA1110E is a low-skew TTLlevel clock buffer chip with multi-phase clock generation. It produces multiple

Contextual Info: Figure 1. Block Diagram GA1110E Multi-Phase Clock Buffer Features * T riQ uint’s GA1110E is a low -skew TTL-level clock buffer chip w ith m ulti-phase clock * generation. It produces m ultiple clock outputs w hich are n orm ally phase- and frequency- Zero-propagation-delay clock

Contextual Info: T R I Q U I N T S E M I C O N D U C T O R, I N C . GA1110E Figure 1. Block Diagram VDD T1 CLKIN FBIN S1 S0 T0 GND 8 7 6 5 4 3 2 1 PHASE-LOCKED LOOP PLL PHASE CONTROL LOGIC Multi-Phase Clock Buffer MUX CONFIGURATION LOGIC Features GND OUTPUT BUFFER OUTPUT

Contextual Info: C O M P U T I N G AND N E T W O R K I N G Figure 1. Block Diagram GA1110E CLKIN GND Multi-Phase Clock Buffer Features * TriQuint's GA1110E is a low-skew TTL-level clock buffer chip with multi-phase clock generation. It produces multiple clock outputs which are normally phase- and frequencysynchronized to a periodic clock input signal. It offers the user the additional flexibility to

Contextual Info: S ’ A’* ' ' " ' , \ C O M P U T I N G VCC T1 E M I C O N D U C T O R , I N C . m AND N E T W O R K I N G CLKIN FBIN S1 SO TO GND G A1110E Multi-Phase Clock Generator/ Low-Skew 771 Clock Buffer Features • Zero propagation delay clock buffer TriQuint’s GA1110E is a low-skew TTLlevel clock buffer chip with multi-phase

Contextual Info: System Timing Products Multi-Phase Clock Buffer GA1110E TriQuint’s GA1110E is a low-skew TTL-level clock buffer chip with multi-phase clock generation. It produces multiple clock outputs which are normally phase- and frequencysynchronized to a periodic clock input signal.

Contextual Info: GA1110E r « M ulti-Phase Clock G enerator Low-Skew TTL Clock Buffer J g a z e lle G eneral Description Features Gazelle’s GA1110E is a low-skew TTL-level clock buffer chip with multi-phase clock generation. It produces multiple clock outputs which are phase and frequency synchronized to a periodic clock

Contextual Info: S E M I C O N D U C T O P I N C 7QS1 :0 M P U T ING AND NETWORKING Figure 1. Block Diagram VOO T1 CLKIN GA1210E FBIN EN2 INV1 Data Sheets Clock Doubter/ Two-Phase Generator Features • 2X clock multiple generator TriQuint’s GA1210E is a low -skew TTL-level clock doubler chip. It produces m ultiple clock

MQUAD

Abstract: 1110E GA1086 GA1086-MC1000 GA1086-MC500 MC500 avw 13
Contextual Info: T R I Q U I N T S E M I C O N D U C T O R , I N C 7Q gt GA1086 Figure 1. Block Diagram 11-Output dock Buffer Features • Operates from 30 MHz to 67MHz • Pin-to-pin output skew of 250 ps max • Period-to-period jitter: 75 ps (typ) microprocessors, with near zero input-to-output delay and very low pin-to-

Contextual Info: VCC T1 C L K IN F B IN EN2 IN V 1 TO GA1210E GND Low-Skew 771 Clock Doubler/ Two-Phase Clock Generator GND QO Q1 02 Q3 TriQuint’s GA1210E is a low-skew TTLlevel clock doubler chip. It produces m ultiple clock outputs, at precisely 2X the input frequency, which are all phasealigned to a periodic clock input signal. The

Contextual Info: T R I 7 Q Q U I N T S E M I C O N D U C T O R , I N C Ö Figure 1. Block Diagram FBIN GA1086 S1 C LK SO NC NC GND 11-Output Clock Buffer Features • Operates from 30 MHz to 67 MHz • Pin-to-pin output skew of 250 p s max • TriQuint’s GA1086 operates from 30 MHz to 67 MHz. This TTL-level clock

Contextual Info: T R I Q U I N T S E M I C O N D U C T O R , I N C 7Q£t GA1210E Figure 1. Block Diagram VD D T1 CLKIN FBIN EN2 INV1 TO GND Clock Doubler / Two-Phase Generator Features • 2X clock multiple generator • Two-phase clock generator T riQ u in t’s G A 1 2 1 OE Is a lo w -s k e w T T L -le v e l c lo c k d o u b le r c h ip . It p ro d u c e s

gazelle microcircuits

Contextual Info: NOM 2 i 1990 GA1210E Low-Skew TTL Clock Doubler Two-Phase Clock G enerator gazelle General Description Features Gazelle’s GA121OE is a low-skew TTL-level clock doubler chip. It produces multiple clock outputs, at precisely 2X the input frequency, which are all phase-aligned to a periodic clock input signal. The

Contextual Info: G A Z E LL E M I C R O C I R C U I T S INC S'ÎE ]> • 3fl3bOB5 OOOOO'îl ô W Ê G k l T^i-OD r m Q A 121OE Low-Skew TTL Clock Doubler Two-Phase Clock Generator J è gazelle General Description Features Gazelle's GA1210E is a low-skew TTL-level clock doubler chip. It

fbii

Abstract: motherboard ga clock generator for 4040
Contextual Info: COMPUTING AND^NET WORKING Figure 1. Block Diagram VDO T1 CLKIN GA1210E FBIN EN2 INVI TO GND Clock Doubler/ Two-Phase Generator Features TriQuint's GA1210E is a low-skew TTL-level clock doubler chip. It produces multiple clock outputs, at precisely 2X the input frequency, which are all phase-aligned to a periodic clock

013Q3

Contextual Info: S COMPUTING AND E M I C O N D U T1 T 0 R , I N C . NETWORKING Figure 1. Block Diagram VDD C CLKIN GA1210E FBIN EN2 IN V I TO GND Data Sheets Clock Doubler/ Two-Phase Generator Features • 2 X clock multiple generator TriQuint's GA1210E is a low-skew TTL-level clock doubler chip. It produces multiple clock

MQUAD

Contextual Info: T R I Q U I N T S E M I C O N D U C T O R, I N C . GA1210E Figure 1. Block Diagram VDD T1 CLKIN FBIN EN2 INV1 T0 GND 8 7 6 5 4 3 2 1 PHASE-LOCKED LOOP PLL Clock Doubler / Two-Phase Generator CONTROL LOGIC MUX DIVIDE LOGIC GND OUTPUT BUFFER OUTPUT BUFFER