IR 10E 1H Search Results

memory 256x1

Abstract: B129 SN74ACT2227 SN74ACT2229
Contextual Info: SN74ACT2227, SN74ACT2229 DUAL 64 x 1 AND DUAL 256 x 1 FIRST-IN, FIRST-OUT MEMORIES SCAS220A - JUNE 1992 - REVISEO AUGUST 1993 Dual Independent FIFOs Organized as: 64 Words by 1 Bit Each - SN74ACT2227 256 Words by 1 Bit Each - SN74ACT2229 Free-Running Read and Write Clocks Can

10H84

Contextual Info: *SYNERGY CLOCK SYSTEM DESIGN A P P L I C A T I O N S BR I EF AB-02 SEMICONDUCTOR INTRODUCTION C lo c k d is trib u tio n is a s ig n ific a n t d e s ig n c h a lle n g e fo r s yste m s o p e ra tin g a b o v e 2 5 M H z . T h e S y n e rg y P E C L se rie s of c lo c k c h ip s s im p lifie s d e s ig n s by s ig n ific a n tly

memory 256x1

Abstract: Texas Instruments TTL handbook b257 B129 B249 SN74ACT2227 SN74ACT2229
Contextual Info: SN74ACT2227, SN74ACT2229 DUAL 6 4 x 1 , DUAL 2 5 6x1 FIRST-IN, FIRST-OUT MEMORIES SCAS220B - JUNE 1992 - REVISED SEPTEMBER 1995 • Dual Independent FIFOs Organized as: 64 Words by 1 Bit Each - SN74ACT2227 256 Words by 1 Bit Each - SN74ACT2229 • Free-Running Read and Write Clocks Can

canon power supply circuit diagrams

Abstract: canon ir power supply circuit diagrams
Contextual Info: TEXAS * INSTR bHE D A S I C / H E M O R Y • OOflPbEM m 2 ■ TIIS SN74ACT2227, SN74ACT2229 DUAL 64 X 1 AND DUAL 256 X 1 FIRST-IN, FIRST-OUT MEMORIES Dual Independent FIFOs Organized As: - 64 Words by 1 Bit Each - SN74ACT2227 - 256 Words by 1 Bit Each - SN74ACT2229

K74 PACKAGE DIAGRAM

Abstract: IR 10e 1h
Contextual Info: = ^~' _ = p r e l im in a r y . ^ SEMICONDUCTOR Features • CY10E494 CY100E494 CY101E494 16,384 x 4 bits organization • Ultra high speed/standard power — tAA = 7 ns — I f E — 180 mA 16,384 x 4 ECL Static RAM • Open emitter output for ease of

J281C

Contextual Info: * SYNERGY ! û fr 1 8 7 b-BIT 2 1 M Ü X• R E G iS f ER -Y 1HOE 1B7 S E M IC O N D U C T O R FEATURES • 1000MHz min. operating frequency ■ Extended 100E V ee range of -4.2V to -5.5V ■ 800ps max. clock to output ■ Single-ended outputs ■ Asynchronous Master Reset

MPR5774X

Abstract: SPR5531 SAA5531 MPG5774X sbr5501 SBG5531 SPY5501 SPG5531 espy SPR5501
Contextual Info: A C INTERFACE INC 10E D | 0GH33Ö3 0Q0G005 T I SUPER BRIGHT LED T - 4-1- 5 ROUND SHAPE 05 T-1 34JTYPE LED Typ# No. fc" : tI 1Ht . i f '• : SPR 5501 IP V ; r- t. E S A A /S A A 5 5 3 1 ESA Y /S A Y 5531 . E S P Y /S P Y 5531 } SPG 5531 1 * ■ - -j ' ”

B25G

Contextual Info: SN74ACT2227, SN74ACT2229 DUAL 6 4 x 1 , DUAL 256 x 1 F I R ST - I N, F I R S T - O U T M E M O R I E S S C A S 220B -JU N E 1 9 9 2 - REVISED SEPTEMBER 1995 • Dual I nde pe n d e n t F I F O s Or g a n i z e d as: 64 W o r d s by 1 Bit Each - S N 7 4 A C T 2 2 2 7

B129

Abstract: B249 SN74ACT2227 SN74ACT2229
Contextual Info: SN74ACT2227, SN74ACT2229 DUAL 64 x 1 AND DUAL 256 x 1 FIRST-IN, FIRST-OUT MEMORIES SCAS220A - JUNE 1992 - REVISED AUGUST 1993 Dual Ind epen den t FIFO s O rg anized as: - 64 W o rd s by 1 Bit Each - S N 74A C T 2227 - 2 5 6 W o rd s by 1 Bit Each - S N 7 4 A C T 2229

TC74VCXR162245FT

Contextual Info: TOSHIBA TC74VCXR162245FT TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC T C 7 4 V C X R 1 6 2 2 4 5 FT LOW-VOLTAGE 16-BIT BUS TRANSCEIVER WITH 3.6V TOLERANT INPUTS AND OUTPUTS The TC74VCXR162245FT is a high performance CMOS 16-bit BUS TRANSCEIVER. Designed for use in 1.8, 2.5 or 3.3 Volt

1r 10e

Contextual Info: K7Q163684A K7Q161884A ADVANCE 512Kx36 & 1Mx18 QDR b4 SRAM TM Document Title 512Kx36-bit, 1Mx18-bit QDRTM SRAM Revision History History Draft Date Remark 0.0 1. Initial document. May 22, 2001 Advance 0.1 1. Icc, Isb addition 2. 1.8V Vddq addition Sep 03, 2001

A301D

Contextual Info: CY10E474 CY100E474 CYPRESS SEMICONDUCTOR • On-chip voltage compensation for im­ proved noise margin Features • 1024 x 4 ECL Static RAM 1024 x 4 -b it organization • Open em itter output for ease of memory expansion • Ultra high speed/standard power

Contextual Info: TOSHIBA TC74VCX16245FT TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC T C 7 4 VC X 1 6245 FT LOW-VOLTAGE 16-BIT BUS TRANSCEIVER WITH 3.6V TOLERANT INPUTS AND OUTPUTS The TC74VCX16245FT is a high performance CMOS 16-bit BUS TRANSCEIVER. Designed for use in 1.8, 2.5 or 3.3

k7r161882b

Abstract: K7R160982B K7R161882B-FC25 K7R163682B K7R163682B-FC16 K7R163682B-FC20 K7R163682B-FC25
Contextual Info: K7R163682B K7R161882B K7R160982B K7R160882B Advance 512Kx36 & 1Mx18 & 2Mx9 & 2Mx8 QDRTM II b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit, 2Mx9-bit, 2Mx8-bit QDRTM II b2 SRAM Revision History Rev. No. 0.0 History Draft Date Remark 1. Initial document. Oct. 17. 2002

Contextual Info: K7I323682M K7I321882M K7I320882M Preliminary 1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDRII CIO b2 SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. October, 22 2001 Advance 0.1 1. Pin name change from DLL to Doff.

IR 10e 7c

Abstract: K7I161882B
Contextual Info: K7I163682B K7I161882B K7I160882B Premilinary 512Kx36 & 1Mx18 & 2Mx8 DDRII CIO b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit, 2Mx8-bit DDRII CIO b2 SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. Oct. 23. 2002 Advance 0.1 1. Add the speed bin -33, -30

K7R323682M-FC20

Abstract: K7R321882M-FC20 K7R321882M-FC16 k7r321882mfc20 K7R323682 K7R323682M-FC16
Contextual Info: K7R323682M K7R321882M K7R320882M Preliminary 1Mx36 & 2Mx18 & 4Mx8 QDRTM II b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit QDRTM II b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. June, 30 2001 Advance 0.1 1. Pin name change from DLL to Doff.

Contextual Info: K7I323684M K7I321884M K7I320884M Preliminary 1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b4 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDRII CIO b4 SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. October, 22 2001 Advance 0.1 1. Pin name change from DLL to Doff.

ddr sram 256mb

Contextual Info: K7J323682M K7J321882M K7J320882M Preliminary 1Mx36 & 2Mx18 & 4Mx8 DDR II SIO b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. July, 15 2001 Advance 0.1 1. Pin name change from DLL to Doff

K7I323682M-FC25

Abstract: K7I321882M-FC16
Contextual Info: K7I323682M K7I321882M K7I320882M Preliminary 1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDRII CIO b2 SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. October, 22 2001 Advance 0.1 1. Pin name change from DLL to Doff.

Contextual Info: K7R163682B K7R161882B K7R160982B K7R160882B Preliminary 512Kx36 & 1Mx18 & 2Mx9 & 2Mx8 QDR TM II b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit, 2Mx9-bit, 2Mx8-bit QDR TM II b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Oct. 17, 2002

K7R643682M-FC20

Abstract: K7R640982M K7R641882M-FC25 K7R643682M-FC25 10D-11 K7R641882M K7R643682M K7R641882M-FC20 K7R643682M-FC16
Contextual Info: K7R643682M K7R641882M K7R640982M K7R640882M Preliminary 2Mx36 & 4Mx18 & 8Mx9 & 8Mx8 QDRTM II b2 SRAM Document Title 2Mx36-bit, 4Mx18-bit, 8Mx9-bit, 8Mx8-bit QDR TM II b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Sep, 14 200 2

Contextual Info: K7R163682B K7R161882B K7R160982B K7R160882B Preliminary 512Kx36 & 1Mx18 & 2Mx9 & 2Mx8 QDR TM II b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit, 2Mx9-bit, 2Mx8-bit QDR TM II b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Oct. 17, 2002

Contextual Info: K7R323682M K7R321882M K7R320982M K7R320882M 1Mx36 & 2Mx18 & 4Mx9 & 4Mx8 QDRTM II b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx9-bit, 4Mx8-bit QDR TM II b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. June, 30 2001 Advance 0.1