JEDEC MO-187 AA Search Results

MO-187-AA Package

Abstract: JEDEC MO-187 MO-187-AA MO-187
Contextual Info: 8-Lead Mini Small Outline Package [MSOP] RM-8 Dimensions shown in millimeters a 3.20 3.00 2.80 8 3.20 3.00 2.80 1 PIN 1 5.15 4.90 4.65 4 0.65 BSC 0.95 0.85 0.75 0.15 0.00 5 1.10 MAX 0.38 0.22 COPLANARITY 0.10 SEATING PLANE 0.23 0.08 8° 0° COMPLIANT TO JEDEC STANDARDS MO-187-AA

ansi-y14.5m-1994

Abstract: MO-187
Contextual Info: Package Information Vishay Siliconix MSOP: 8-LEADS POWER IC ONLY JEDEC Part Number: MO-187, (Variation AA and BA) (N/2) Tips) 2X 5 N N-1 A B C 0.20 0.60 0.48 Max Detail “B” (Scale: 30/1) Dambar Protrusion E 0.50 1 2 0.60 N/2 0.08 M C B S b Top View A S

5922

Abstract: 72817 ansi-y14.5m-1994 MO-187 JEDEC MO-187 aa MO-187-AA Package
Contextual Info: Package Information Vishay Siliconix MSOP: 10-LEADS POWER IC ONLY JEDEC Part Number: MO-187, (Variation AA and BA) (N/2) Tips) 2X 5 N N-1 A B C 0.20 0.60 0.48 Max Detail “B” (Scale: 30/1) Dambar Protrusion E 0.50 1 2 0.60 N/2 0.08 M C B S b Top View

5867

Abstract: 71244 ansi-y14.5m-1994 MO-187 JEDEC MO-187 ba JEDEC MO-187 Variation BA mo187 MO-187-AA Package
Contextual Info: Package Information Vishay Siliconix MSOP: 8−LEADS JEDEC Part Number: MO-187, Variation AA and BA (N/2) Tips) 2X 5 A B C 0.20 N N-1 0.60 0.48 Max Detail “B” (Scale: 30/1) Dambar Protrusion E 1 2 0.50 N/2 0.60 0.08 M C B S b A S 7 Top View b1 e1 With Plating

ansi-y14.5m-1994

Abstract: MO-187 10-LEADS JEDEC MO-187 Variation BA B.A BSc
Contextual Info: Package Information Vishay Siliconix MSOP: 10−LEADS JEDEC Part Number: MO-187, Variation AA and BA (N/2) Tips) 2X 5 A B C 0.20 N N-1 0.60 0.48 Max Detail “B” (Scale: 30/1) Dambar Protrusion E 1 2 0.50 N/2 0.60 0.08 M C B S b A S 7 Top View b1 e1 With Plating

cqx 87

Abstract: germanium AEG Thyristor T 558 F TDA 2516 bu208 bf506 la 4430 BF963 TDA1086 transistor bf 175
Contextual Info: Page Contents Diodes 8 Transistors 15 Optoelectronic Devices 24 Integrated Circuits 33 1 Contents, alpha-numeric Type Page AA 112 AA113 AA117 AA 118 AA119 AA 132 AA 133 AA 134 AA 137 AA 138 12 12 8 12 12 8 8 8 12 12 BA 111 BA 121 BA 124 BA 125 BA 147/. BA 157

MO-187

Abstract: R005 JEDEC MO-187
Contextual Info: R E V I S I O N S REV A D E S C R 1P T I O N RELEASE TO DOC U ME NT E.C. M . DATE BY/APP'D 1262 11/18/2003 H R//TLSN CONTROL [ 1 . 85] 8X .040 — [ 1.02] ( 8X .016 ) [ 0 . 41] ( 6X .026 ) [0.65] RECOMMENDED LAND PATTERN NOTES: UNLESS OTHERWI SE SPECIFIED

MO-187-AA-T Package

Contextual Info: Preliminary data HiPerFAST IGBT IXGK80N60A 600 V 80 A 2.7 V 275 ns VCES IC25 V CE sat % Symbol TestC onditions v CES Tj = 25°C to 150 °C 600 V VCGR T j = 25°C to 150°C; RGE = 1 MO 600 V V GES Continuous ±20 V V 3 EM Transient ±30 V T c = 25°C, limited by leads

TLV2252

Abstract: TLV2252AID TLV2254 TLV2432 TLV2442
Contextual Info: TLV225x, TLV225xA Advanced LinCMOS RAIL-TO-RAIL VERY LOW-POWER OPERATIONAL AMPLIFIERS SLOS185C – FEBRUARY 1997 – REVISED – MARCH 2001 D D D D D D Output Swing Includes Both Supply Rails Low Noise . . . 19 nV/√Hz Typ at f = 1 kHz Low Input Bias Current . . . 1 pA Typ

G 50N60

Abstract: 50N60 igbt 100a 50n50 IXGH50N60B
Contextual Info: HiPerFAST IGBT with Diode V V CES IXGK 50N50BU1 IXGK 50N60BU1 ^C 2 5 500 V 75 A 600 V 75 A ^ C E s a t 2.3 V 2.5 V 100ns 120ns Combi Pack Preliminary data Symbol Test Conditions Maximum Ratings 50N50 vCES V C GR VGES VGEM 'c o ' cm 50N60 Tj = 25°C to 150°C

TSMA13A

Abstract: sm41 BRIDGE-RECTIFIER 10v 1A bq 738 TSMA39A TSMA9.1A TSMA10 TSMA10A TSMA11 TSMA11A
Contextual Info: GENL IN S T R / 3fiE II • POIilER 3810137 000m,=il 1 HlSIC T-//-23 « » « P *R ♦E * L* I* IVI • I * N ♦ A *R ♦ Y ♦ ♦ * ♦ ♦ ♦ TSMA SERIES SURFACE MOUNT TRANSIENT VOLTAGE SUPPRESSOR VOLTAGE - 6.8 - 200 Volts % FEATURES ♦ For surface mounted applications

FEPROM

Abstract: YL41 10B60 LM 10841 7v71 10B28 U131-1-2
Contextual Info: PRELIM INARY VF1 FPGA Family B EY O N D P ER F O R M A N C E FEATURES AND BENEFITS ♦ The industry’s first Variable-Grain-Architecture enables high-density, high-performance designs for a wide range of applications — Architecture adapts to logic to enable synthesis-friendly, high-performance designs

DS040

Abstract: l6232
Contextual Info: PRELIMINARY VF1 FPGA Family BEY O N D PER FO RM AN C E FEATURES AND BENEFITS P u b lic atio n # V F 1003-D S-1 A m en d m en t/O Issu e D ate: N o v e m b e r 1 9 9 8 VF1 FPGA Family ♦ The industry's first Variable-Grain-Architecture enables high-density, high-performance

2u20 diode

Abstract: 2U39 diode 1N4C07 IN6016 IN4688 1N4C03 1N4C02 HRG1000 1N1989B 1N218
Contextual Info: CODI Semiconductor, Inc m PRODUCT CATALOG Serving the Industry for over 25 years. SILICON DIODES • • • • • • • Zener and avalanche regulator diodes Temperature compensated zener reference diodes Forward regulator diodes Low leakage diodes Voltage variable capacitors

DDR2-400

Abstract: DDR2-533 DDR2-667 MO-224 MT16HTS25664HY-667 PC2-3200 PC25300 MT47H128M8BT HTS16C256 mt47
Contextual Info: 2GB: x64, DR 200-Pin DDR2 SDRAM SODIMM Features DDR2 SDRAM SODIMM MT16HTS25664H – 2GB For component specifications, refer to Micron’s Web site: www.micron.com/products/ddr2sdram Features Figure 1: • 200-pin, small outline, dual in-line memory module

Contextual Info: 0: 30 PM PM8355 QuadPHY II Datasheet Released Mo nd ay ,0 QuadPHY® II 9M ay ,2 00 5 11 :3 PM8355 d of ag er rt on Four Channel 2.125-3.125 Gbits/s SERDES by sa tis h Datasheet Do wn lo ad ed Proprietary and Confidential Released Issue 7: June 2003 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

Contextual Info: 9: 07 PM PM8355 QuadPHY II Datasheet Released ug Mo nd ay ,0 1A QuadPHY® II us t, 20 05 10 :1 PM8355 rtm in er In co n Four Channel 2.125-3.125 Gbits/s SERDES Proprietary and Confidential Released Issue 8: July 2005 Do wn lo ad ed by C on te n tT ea m of

minidimm

Abstract: DDR2-400 DDR2-533 DDR2-667 PC2-3200 PC2-5300
Contextual Info: 1GB: x72, DR 244-Pin DDR2 VLP Reg. MiniDIMM Features DDR2 VLP Registered MiniDIMM MT18HVS12872(P)K – 1GB For component specifications, refer to Micron’s Web site: www.micron.com/products/ddr2sdram Features Figure 1: • 244-pin, very low profile mini dual in-line memory

Contextual Info: PM4328 TECT3 STANDARD PRODUCT DATASHEET ISSUE 1 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER :3 5: 17 AM PMC-2011596 ep 2S Mo nd ay ,2 TECT3 te m be r, 20 03 07 PM4328 DATASHEET PROPRIETARY AND CONFIDENTIAL ISSUE 1: AUGUST 2001 Do wn lo ad ed by Co nt en

minidimm

Contextual Info: 256MB, 512MB: x72, SR 244-Pin DDR2 Reg. MiniDIMM Features DDR2 SDRAM Registered MiniDIMM MT9HTF3272(P)K – 256MB MT9HTF6472(P)K – 512MB For component specifications, refer to Micron’s Web site: www.micron.com/products/ddr2sdram Features Figure 1: • 244-pin, mini dual in-line memory module

MT36HTS1G72FY667A1D4

Abstract: RE87 E40002
Contextual Info: 8GB x72, DR 240-Pin DDR2 SDRAM FBDIMM Features DDR2 SDRAM FBDIMM MT36HTS1G72F – 8GB For the latest data sheet, refer to Micron’s Web site: www.micron.com Features Figure 1: • 240-pin DDR2 fully buffered dual in-line memory module (FBDIMM) • Fast data transfer rates: PC2-4200 and PC2-5300

TFK 404

Abstract: T1S58 BCI83L Germanium diode OA 182 TFK diode transistors 2n 945 v744 akai amplifier tis62 BCI09
Contextual Info: S IL IC O N T R A N S IS T O R S PN P Fast Switches N PN Fast: Switches D e v ic e B S X 27 T IS 4 4 T IS 45 T IS 46 T IS 47 T IS 48 T IS 49 Page 96 166 168 170 172 172 174 D e v ice Page T I S 51 T IS 52 T IS 55 2N 706A 2N 708 2N 753 2N 914 178 180 185 317

MV-S100649-00

Abstract: Marvell 88e1111 register map Marvell PHY 88E1111 Marvell PHY 88E1111 application note 88E1111 88E1111 PHY registers map marvel phy 88e1111 reference design Marvell 88E1111 application note 88E1111 full Marvell 88E1111
Contextual Info: 7v u3 M 1z AR zf VE nu LL a-e CO 468 NF 1d ID ge EN * M 7v TI ar u3 AL ve M 1z , U ll S AR zf ND em VE nu ER ic LL a-e NDond CO 468 A# uc NF 1d 02 tor, ID ge EN * M 13 In 03 c. TI ar AL ve , U ll S ND em ER ic NDond A# uc 02 tor, 13 In 03 c. MARVELL CONFIDENTIAL

M3-12H

Abstract: SMD FUSE 140D pmc-2001578 179d 203d 332h b4 109d PMC-2020180 312H PM4318
Contextual Info: :4 4: 11 AM Octal E1/T1/J1 Line Interface Device Telecom Standard Product Data Sheet Released ua ry ,2 00 3 05 PM4318 Mo nd ay ,0 6J an OCTLIU Data Sheet Proprietary and Confidential Released Issue No. 6: May 2002 Do wn lo ad ed by ah m ed m et wa ly of sil