LC112 Search Results

Contextual Info: UNISONIC TECHNOLOGIES CO., LTD LC1126 Preliminary LINEAR INTEGRATED CIRCUIT ULTRA LOW OUTPUT VOLTAGE LINEAR N-FET CONTROLLER „ 5 6 DESCRIPTION The UTC LC1126 is an ultra low output voltage linear N-FET controller designed to provide well supply voltage for

Contextual Info: UNISONICTECHNOLOGIESCO., LTD LC1126 Preliminary LINEAR INTEGRATED CIRCUIT U LT RA LOW OU T PU T V OLT AGE LI N EAR N -FET CON T ROLLER 5 4 6 ̈ DESCRI PT I ON The UTC LC1126 is an ultra low output voltage linear N-FET controller designed to provide well supply voltage for

Contextual Info: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

Contextual Info: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

LCV112A

Contextual Info: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET SCAS289I – JANUARY 1993 – REVISED MARCH 2002 D D D D D D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Inputs Accept Voltages to 5.5 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C

Contextual Info: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

Contextual Info: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

74HC09

Abstract: K2108
Contextual Info: r z T S G S -T H O M S O N M 5 4 H £ 2 2 [M r a [E L H @ [* S M 74HC 09 QUAD 2-INPUT AND GATE OPEN DRAIN HIGHSPEED 6 ns (TYP.) A T V cc = 5 V LOW POWER DISSIPATION Ice = 1 (iA (MAX.) AT Ta = 25 "C HIGH NOISE IMMUNITY V n ih = V n il = 28 % Vcc (MIN.)

34AE

Contextual Info: Qualification Test Report 501-78143 Was TR-98071 19MAY09 Rev. A1 認定試験報告書 Super Seal Connector SUPER SEAL コ ネ ク タ 1. 目的 製品規格 108-78140 (旧仕様書番号PS-1171)に基づきSUPER SEALコネクタ60極ASS’Y の総合評価試験を行う。

5D10L

Abstract: ND R315 F001B schematic atx 2.03 P4 CC186 7805 stmicroelectronics 2n2222 h 331 74fct521atq 2N3904 B48 712C
Contextual Info: 1 2 3 4 5 6 CONSUMER-SBD D D Evaluation board based on STPC CONSUMER-S/ELITE/CONSUMER-II full compatibility 1.1 SA000106 October 12, 2000 C C BOARD DESCRIPTION: FILE NAME - Motherboard in ATX format. - STPC interfaces : * Standard Super-VGA monitor output

ND R315

Abstract: schematic atx 2.03 P4 fdc37b782 5K58 4AC125 RTCO ac9 AD9142 C226 7805 DER-20 RP5A
Contextual Info: 1 2 3 4 5 6 RDCONSUMER-S D D Reference design based on STPC CONSUMER-S 1.1 SAA00029AAXX JULY 21, 2000 C C BOARD DESCRIPTION: FILE NAME - Motherboard in ATX format. - STPC interfaces : * Standard Super-VGA monitor output * 3 PCI slots * 3 ISA slots - Super I/O interfaces :

LC112A

Abstract: LVC112A A115-A C101 SN74LVC112A SN74LVC112AD
Contextual Info: SN74LVC112A DUAL NEGATIVEĆEDGEĆTRIGGERED JĆK FLIPĆFLOP WITH CLEAR AND PRESET SCAS289K − JANUARY 1993 − REVISED OCTOBER 2003 D D D D D D D D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 4.8 ns at 3.3 V

Contextual Info: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

Contextual Info: GENERAL PURPOSE POWER MANAGEMENT QUICK SELECTION GUIDE Switching Regulators, LDOs, Power Modules, FET Drivers, Analog Controllers INTERSIL POWER MANAGEMENT SOLUTIONS A HERITAGE OF POWERING INNOVATION Learn how Intersil’s power management technologies have

A115-A

Abstract: C101 SN74LVC112A SN74LVC112AD LC112 CPD14
Contextual Info: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

74HC09

Abstract: 74HC09B
Contextual Info: SGS-THOMSON Rffl0» [iy iM !0 gi ms4HC09 M74HC09 QUAD 2-INPUT AND GATE (OPEN DRAIN) • HIG HSPEED 1pd = 6 ns (TYP.) AT Vcc = 5 V ■ LOW POWER DISSIPATION Ice = 1 JiA (MAX.) A T T a = 25°C ■ HIGH NOISE IMMUNITY V nih = V n il = 28 % V cc (MIN.) ■ OUTPUT DRIVE CAPABILITY

IC 74LS00

Abstract: 74LS00 gate diagram nand IC TTL 74LS00 M74HCT00
Contextual Info: S G S -T H O M S O N jL iM s iO (g S M 5 4 H C T oo M74HCT00 QUAD 2-INPUT NAND GATE • H IG H S P E E D tp D = 12 ns (TYP.) AT V c c = 5 V ■ LO W PO W ER DISSIPATION Ice = 1 |iA (M AX.) A T T a = 2 5 °C ■ C O M P A TIB LE W ITH TTL O U TP U TS V ih = 2V (MIN.) V il = 0.8V (MAX)

Contextual Info: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

Contextual Info: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

Programmer Kit

Abstract: User Guides LED Dot Matrix vhdl code 7 segment LED display project counter lc48 GCLR MARK 84 Pin PLCC Socket diode D6E dot matrix printer circuit diagram datasheet header 20X2
Contextual Info: CPLD Development/Programmer Kit . User Guide -2 xxxxA–XXXXX–xx/xx CPLD Development/Programmer Kit User Guide Table of Contents Section 1 Introduction . 1-1

A115-A

Abstract: C101 SN74LVC112A SN74LVC112AD LC112A
Contextual Info: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289K – JANUARY 1993 – REVISED FEBRUARY 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

EL B17 C242

Abstract: EL B17 C244 SA8 357 man7 ND R315 md33 2n2222 -331 MD243 EVAL120 b30 c250
Contextual Info: 1 2 3 4 5 6 CONSUMER-SBD D D Evaluation board based on STPC CONSUMER-S/ELITE/CONSUMER-II full compatibility 1.0 Reference number JANUARY 15, 2000 C C BOARD DESCRIPTION: FILE NAME - Motherboard in ATX format. - STPC interfaces : * Standard Super-VGA monitor output

Contextual Info: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

74LS06D

Abstract: IC TTL 74LS06 54hct08 74ls06 dip14 ttl 74ls06 74HCT08 4HCT08 M74HCT08
Contextual Info: S G S -T H O M S O N jL iM s iO (g S 4HCT08 M74HCT08 m s QUAD 2-INPUT AND GATE • HIG HSPEED tpD = 12 ns (TYP.) AT Vcc = 5 V ■ LOW POWER DISSIPATION Ice = 1 |iA (MAX.) A T T a = 25°C ■ COMPATIBLE WITH TTL OUTPUTS V ih = 2V (MIN.) V il = 0.8V (MAX)