LH532100BD Search Results

A1SH

Abstract: 32DIP 32-PIN LH532100B-1 A14C
Contextual Info: LH532100B-1 FEATURES CMOS 2M 256K x 8 Mask-Programmable ROM PIN CONNECTIONS • 262,144 words x 8 bit organization • Access time: 120 ns (MAX.) 32-PIN DIP 32-PIN SOP TOP VIEW f \ O E ^ O E i/D C C • Static operation • TTL compatible I/O • Three-state outputs

536G

Abstract: LH534600
Contextual Info: MEMORIES • Mask ROMs Process Capacity * Configuration words X bits Pinout Access time Model No. (ns) MIN. Supply current (mA) MAX. Supply voltage (V) (ns) MAX. User's No. Cycle tima Package 256k 32k X 8 J LH53259D/N/T L H 5359X X 150 25 5 ± 10% 28DIP/28SOP/28TSOP(I)

Contextual Info: CM O S 2M 256K x 8 Mask-Programmable ROM FEATURES DESCRIPTION • 262,144 x 8 bit organization T h e LH 5 321 00 B is a m ask-program m able R O M organized a s 262,144 x 8 bits. It is fabricated using silicon-gate C M O S p rocess technology. • Access time: 120/150 ns (MAX.)

Contextual Info: C M OS 2M 256K x 8 M ask-Program m able ROM FEATURES • 262,144 x 8 bit organization • Access time: 120/150 ns (MAX.) • Low power consumption: Operating: 275 mW (MAX.) DESCRIPTION The LH532100B is a mask-programmable ROM organized as 262,144 x 8 bits. It is fabricated using

J-1100

Contextual Info: LH532100B-1 FEATURES • 262,144 words x 8 bit organization CMOS 2M 256K x 8 MROM PIN CONNECTIONS 32-PIN DIP 32-PIN SOP TOP VIEW • Access time: 120 ns (MAX.) f • Three-state outputs • Single +5 V power supply • Power consumption: Operating: 275 mW (MAX.)

41C1000

Abstract: fujitsu 814100 TC 55464 toshiba HN62304 hn623257 658128 816b 41c464 hn62324 M7202A
Contextual Info: MEM ORY ICs FUNCTION GUIDE 3. C R O S S REFERENCE GUIDE 3.1 DRAM Density Org. Samsung Mode Toshiba Hitachi Fujitsu H M 51 256 M B 81256 NEC Oki 64K X 1 Page K M 416 4 25 6 K X 1 F. Page KM 41C256 TC 51256 Nibble KM 41C257 TC51257 S. C olu m n KM 41C258 TC 51258

DIC14

Contextual Info: LH532100B-1 FEATURES • 262,144 words x 8 bit organization • Access time: 120 ns MAX. CMOS 2M (256K x 8) M a sk-P ro g ra m m a b le ROM PIN CONNECTIONS 32-PIN DIP 32-PIN SOP TOP VIEW s • Three-state outputs • Single +5 V power supply • Power consumption:

Contextual Info: CMOS 2M 256K x 8 MROM FEATURES DESCRIPTION • 262,144 w ords x 8 bit organization • Access tim e: 150 ns (MAX.) The LH532100B is a 2M-bit mask-programmable ROM organized as 262,144 x 8 bits. It is fabricated using silicon-gate CMOS process technology.

41C464

Abstract: 41C1000 TC55B8128 424170 NEC CY70199 44C1000 IOT7164 HN62308BP HN62404P TC5116100
Contextual Info: MEM ORY ICs CRO SS REFERENCE GUIDE 3. C R O SS REFERENCE GUIDE 3.1 DRAM Density 25 6 K Org. X 1 X 4 1M X 1 X 4 4M X 1 X 4 x8 16M M ode Sa m su n g F. Page KM 41C256 TC 51256 N ibble KM 41C257 TC 51257 S. C o lu m n KM 41C258 TC 51258 H M 51 258 MB81258 F. Page

K93C46

Abstract: 93cs46n MB832001 hn62308 41C1000 93C46LN 41464 hn623257 HM63832 DT71256
Contextual Info: MEMORY ICs CROSS REFERENCE GUIDE 3. CROSS REFERENCE GUIDE 3.1 DRAM D ensity 256K X 1 F. P a g e KM 41C 256 TC 51256 X 1 X 4 4M X 1 X 4 , 1 6M To sh iba M od e X 4 1M Sam su ng Org. H ita ch i Fu jitsu HM 51256 M B81256 NEC /iP D 4 1 2 5 6 N ib b le KM 41C 257

TC55B8128

Abstract: KM23C4000AG TC534000AF HN62308BP TC551632 hitachi cross mb83 68512U HITACHI 64k DRAM TC55B4256
Contextual Info: MEMORY ICs CROSS REFERENCE GUIDE 3. CROSS REFERENCE GUIDE 3.1 DRAM D ensity 2 56 K 1M Org. x1 Toshiba F Page T C 51256 N ib b le K M 4 1C 2 5 7 T C 51257 H ita ch i H M 51 2 5 6 — F u jitsu M B 8 12 5 6 M B 8 12 5 7 NEC /P D 41256 — Oki M S M 5 1C 2 5 6

lh5359

Abstract: e5bx
Contextual Info: Ffe MASK ROM * ★ • MASK ROMs New product Under development * Features • Product lineup covers 11 capacity ranges from 256 k-bit to 128 M-bit. • Product variations with 3 types o f pinout including JEDEC standard EPROM, Mask ROM specific and Flash memory compatible pinout.

32DIP

Abstract: 32-PIN LH532100B 277A5
Contextual Info: LH532100B CMOS 2M 256K x 8 MROM FEATURES DESCRIPTION • 262,144 words × 8 bit organization The LH532100B is a 2M-bit mask-programmable ROM organized as 262,144 × 8 bits. It is fabricated using silicon-gate CMOS process technology. PIN CONNECTIONS 32-PIN DIP

DIC20

Contextual Info: CMOS 2M 256K x 8 MROM FEATURES DESCRIPTION • 262,144 words x 8 bit organization The LH532100B is a 2M-bit m ask-program m able ROM organized as 262,144 x 8 bits. It is fabricated using silicon-gate CMOS process technology. • Low-power consumption: Operating: 275 mW (MAX.)

500-101

Contextual Info: CMOS 2M 256K x 8 Mask-Programmable ROM FEATURES DESCRIPTION • 262,144 words x 8 bit organization The LH532100B is a 2M-bit mask-programmable ROM organized as 262,144 x 8 bits. It is fabricated using silicon-gate CMOS process technology. • Access time: 150 ns (MAX.)

ICE ICC3

Abstract: sharp mask rom
Contextual Info: CMOS 2M 256K x 8 Mask Programmable ROM FEATURES • 262,144 x 8 bit organization • Access time: 120/150 ns (MAX.) • Low power consumption: DESCRIPTION The LH532100B is a mask programmable ROM organized as 262,144 x 8 bits. It is fabricated using silicon-gate CMOS process technology.

lh5s4

Abstract: LH-MN47XX lh5s4axx LH5359 LH5s lh5317 LH532CXX 32DIP
Contextual Info: MEMORIES • JEDEC Standard EPROM Pinout • Low voltage operation 3 V, 1.8 V Access time Bit Capacity configuration 1M 2M 4M Model No. LH53V1ROON/T LH53V2R00AN/AT LH53V2T00E LH53V2YOONÆ LH53V4T00E LH53V4R00AN/AT LH53V4Y00NÆ x 8 x 8 x 8 User’s No. Supply

32DIP

Abstract: 32-PIN LH532100B-1 532100B1-6 timing DIAGRAM OF ROM
Contextual Info: LH532100B-1 FEATURES • 262,144 words x 8 bit organization • Access time: 120 ns MAX. • Static operation CMOS 2M (256K × 8) Mask-Programmable ROM PIN CONNECTIONS 32-PIN DIP 32-PIN SOP TOP VIEW OE1/OE1/DC 1 32 VCC A16 2 31 DC • TTL compatible I/O

32DIP

Abstract: 32-PIN LH532100B CE-2212
Contextual Info: LH532100B CMOS 2M 256K x 8 Mask-Programmable ROM FEATURES DESCRIPTION • 262,144 words × 8 bit organization The LH532100B is a 2M-bit mask-programmable ROM organized as 262,144 × 8 bits. It is fabricated using silicon-gate CMOS process technology. PIN CONNECTIONS

Contextual Info: LH532100B-1 FEATURES • 262,144 words x 8 bit organization CMOS 2M 256K x 8 MROM PIN CONNECTIONS 32-PIN DIP 32-PIN SOP TOP VIEW • Access time: 120 ns (MAX.) / O E ^Ô Ë ^D C H • Static operation • TTL compatible I/O • Three-state outputs • Power consumption:

Contextual Info: CMOS 2M 256K x 8 Mask-Programmable ROM FEATURES • 2 6 2 ,1 4 4 x 8 bit organization • Access time: 120/150 ns (M AX.) • Low-power consumption: DESCRIPTION The LH532100B is a mask-programmable ROM organized as 262,144 x 8 bits. It is fabricated using

32DIP

Abstract: 32-PIN LH532100B-1
Contextual Info: LH532100B-1 FEATURES • 262,144 words x 8 bit organization • Access time: 120 ns MAX. • Static operation CMOS 2M (256K × 8) MROM PIN CONNECTIONS 32-PIN DIP 32-PIN SOP TOP VIEW OE1/OE1/DC 1 32 VCC A16 2 31 DC • TTL compatible I/O A15 3 30 A17 4 29