LH5496 Search Results

n 18k U

Abstract: 132-QFP
Contextual Info: MEMORIES FIFO Memories T ype C a p a c ity Shallow Asynch. B it c o n fig u ra tio n Model No. O p e ra tin g fre q u e n c y MHz 25 64x8 LH5481 64x9 LH5491 35 0.5k A c c e s s tim e (n s ) 15 D eeper Asynch 20 25 35 50 LH5496 4.5k 512x9 9k 1k x 9 LH540202

Contextual Info: THE SHARP WAY TO CHOOSE A FIFO START FIFO DEPTH 512: ( LH5496 ) (LH 540215) 1K: (LH 5 402 02) (LH 5 402 25) 36/32 1S/16 36/32 <-» 9/8 36/32 -»18/16, 18/16 -> 36/32 36/32 -* 9/8, 9/8 -> 36/32 18/16-»9/8, 9/8 -*18/16 ( LH543621) ( l H543620)3' v H j? 4?.1.1.'

Contextual Info: LH5496/96H FEATURES • Fast Access Times: 15 720/25/35/50/65/80 ns CMOS 5 1 2 x 9 FIFO PIN CONNECTIONS 28-PIN PDIP TOP VIEW • Full CMOS Dual Port Memory Array • Fully Asynchronous Read and Write • Expandable-in Width and Depth W C 1• 28 —I ^ c c

32-PIN

Abstract: IDT7201 LH5496 LH5496H
Contextual Info: LH5496/96H FEATURES • Fast Access Times: 15 */20/25/35/50/65/80 ns CMOS 512 x 9 FIFO PIN CONNECTIONS 28-PIN PDIP TOP VIEW 1 28 VCC D8 2 27 D4 D3 3 26 D5 D2 4 25 D6 D1 5 24 D7 • Full, Half-Full, and Empty Status Flags D0 6 23 FL/RT • Read Retransmit Capability

32-PIN

Abstract: IDT7201 LH5496 LH5496H 32PLCC
Contextual Info: LH5496/96H FEATURES • Fast Access Times: 15 */20/25/35/50/65/80 ns CMOS 512 x 9 FIFO PIN CONNECTIONS 28-PIN PDIP TOP VIEW 1 28 VCC D8 2 27 D4 D3 3 26 D5 D2 4 25 D6 D1 5 24 D7 • Full, Half-Full, and Empty Status Flags D0 6 23 FL/RT • Read Retransmit Capability

organizational structure samsung

Abstract: CYPRESS SAMSUNG CROSS REFERENCE DALLAS cross reference VITELIC MK4501 ic cross reference book CY7C408 mosel KM75C02
Contextual Info: FIFO Cross Reference FIFO CROSS REFERENCE ORGANIZATIONAL STRUCTURE SHARP MODEL * COMPETITIVE VENDOR 256 X 36 X 2 LH5420 LH5481 64 X 8 64 X 9 LH5491 4,096 X 9 4,096 X 9 4,096 X 9 1,024 X 9 2,048 X 9 X LH5493 LH5494 LH5496/96H 512 X 9 4.096 LH5492 9 LH5497/97H

S496

Contextual Info: LH5496 FEATURES • • Fast Access Times: 15/20/25/35/50/65/80 ns PIN CONNECTIONS TO P VIEW 28-PIN PDIP Fully Asynchronous Read and Write • Expandable-in Width and Depth • Full, Half-Full, and Empty Status Flags • Read Retransmit Capability • TTL Compatible I/O

lh5496

Contextual Info: LH5496 FEATURES • Fast Access Times: 15/20/25/35/50/65/80 ns CMOS 51 2x9 FIFO PIN CONNECTIONS 28-PIN PDIP TOP VIEW W C 1• • Full CMOS Dual Port Memory Array D .C o3C • Fully Asynchronous Read and Write &2 C 4 D, C 5 • Expandable-in Width and Depth

Contextual Info: LH5496/96H FEATURES • Fast Access Times: 15 720/25/35/50/65/80 ns CMOS 5 1 2 x 9 FIFO PIN CONNECTIONS 28-PIN PDIP TOP VIEW • Full CMOS Dual Port Memory Array • Fully Asynchronous Read and Write • Expandable-in Width and Depth • Full, Half-Full, and Empty Status Flags

Contextual Info: LH5496/96H FEATURES • Fast Access Times: 15 720/25/35/50/65/80 ns • Full CMOS Dual Port Memory Array • Fully Asynchronous Read and Write • Expandable-in Width and Depth • Full, Half-Full, and Empty Status Flags • Read Retransmit Capability •

AM7204

Abstract: IC Works cross DALLAS cross reference CY7C408
Contextual Info: FIFO Cross Reference FIFO CROSS REFERENCE ORGANIZATIONAL STRUCTURE COMPETITIVE VENDOR SHARP MODEL ' Cypress [ CY7C408 AMD i CY7C409 _ Cypress ACCESS TIME SHARP PACKAGE OPTIONS 35/25/15 MHz -h - Cypress LH5496/96H COMPETITIVE MODEL 35/25/15 MHz Am7201 DIP/PLCC

Contextual Info: MEMORIES FIFO M emories ★Under developm ent Type Capacity Configuration Operating frequency MHz MAX. Model No. 25 —i 35 Access time(ns) 15 20 25 35 Package SKDIP QFJ 28 28 28 28 28 28 32 — 28 28 32 28 32 28 32 28 32 50 DIP LH5481 LH5491 j — LH5496

Contextual Info: LH5496/96H FEATURES • Fast Access Times: 15 720/25/35/50/65/80 ns CMOS 512x9 FIFO PIN CONNECTIONS TOP VIEW 28-PIN PDIP w □ 1• 28 □ Vcc D0 C 2 27 □ d4 d3 C 3 26 □ d5 d2 C 4 25 D Dß d, L 5 24 □ D0 C 6 23 □ FL/RT xi C 7 22 3 RS L 8 21 □ ËF

Contextual Info: LH5496/96H FEATURES • Fast Access Times: 15 720/25/35/50/65/80 ns CMOS 512x9 FIFO PIN CONNECTIONS T O P V IE W 2 8 - P IN P D IP • Full CMOS Dual Port Memory Array • Fully Asynchronous Read and Write • Expandable-in Width and Depth • Full, Half-Full, and Empty Status Flags

Contextual Info: LH540206 FEATURES • Fast Access Times: 20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing • Expandable in Width and Depth • Full, Half-Full, and Empty Status Flags

lh57257

Abstract: IR2E31 IR2E01 IR2C07 IR2E27 IR2E24 IR2E19 IR2E31A IR3n06 IR2E02
Contextual Info: Index Model No. ARM7D CPU Core Bi-CMOS 1 27 40,42 _ _ CMOS CMOS CMOS CMOS CMOS 4A 5A 8 A AH D ID1 Series ID2 Series 40,42 40.42 40,42 40,42 40 B ü.’1*"! 14,15 14 m IR2339 IR2403 IR2406 IR2406G IR2410 IR2411 IR2415 IR2419 IR2420 IR2422 IR2425 IR2429

toshiba 32k*8 sram

Abstract: M5M23C100 M5M5265 seeq DQ2816A M5M23C400 MB832001 HITACHI 64k DRAM TC511000 KM41C464 TC51464
Contextual Info: FUNCTION GUIDE MEMORY ICs 3. CROSS REFERENCE GUIDE 3.1 DRAM Density 64 K X 1 256K X 1 X4 1M X X 4M X X 3.2 Mode Org. 1 4 1 4 Samsung Toshiba Hitachi Fujitsu NEC MSM3764 KM4164 Page Okl F. Page KM41C256 TC51256 Nibble KM41C257 TC51257 HM51256 S. Column KM41C258

20M32

Abstract: u1520
Contextual Info: CO FIFO BUFFER MEMORY/IC MEMORY CARD ★ U n d e r d e v e lo p m e n t • FIFO BUFFER MEMORIES ♦ Features • It is applicable to communication and OA equipment, as a data buffer between systems operating at different speeds. Bit Capacity configuration

Contextual Info: LH540206 FEATURES • Fast Access Times: 20/25/35/50/65/80 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing • Expandable in Width and Depth • Full, Half-Full, and Empty Status Rags

CM3P67202AL25

Abstract: AM7202A-35RC AM7205 IDT7201SA 67202 CMS1-67204 AM7205A-25RC AM7201-50RC DS2009R IDT7202SA50TP
Contextual Info: FIFO MATRA MHS FIFO Cross Reference AMD AMD Part-Number AM7201-25JC AM7201-25RC AM7201-35JC AM7201-35RC AM7201-50JC AM7201-50RC AM7202A-25JC AM7202A-25RC AM7202A-35JC AM7202A-35RC AM7202A-50JC AM7202A-50RC AM7203A-25JC AM7203A-25RC AM7203A-35JC AM7203A-35RC

LQ070T5BG01

Abstract: LM24P20 LM162KS1 BSCR86L00 IR2C07 LM5Q31 IR3Y29B BSCU86L60 lq6bw lq6bw506
Contextual Info: INDEX 1 0 4 - 1 0 9 _ DC_ GL1PR112.69 GL3KG63. 66 GL5EG41.66 1 0 4 - n 0 5 O o c .113 DC1B1CP. 100 GL1PR135.69 GL3KG8. 66

IR3Y29B

Abstract: ir3y26a1 IR4N IR3T24N IR3C08N ir2c53 ir2c05 li3301 IR3Y08 IR2E02
Contextual Info: Index Model No. IR3T ARM710 ARM7DI ARM7DM ARM7TDMI ARM7TDMI-SPL ARM8 ARM810 CMOS CMOS CMOS CMOS F series G series J series K series ID22 series ID222XX ID223XX ID224XX ID226XX ID227XX ID229XX ID22DXX ID22FXX ID22HXX ID240 series ID240DXX ID240EXX ID240GXX

41C1000

Abstract: fujitsu 814100 TC 55464 toshiba HN62304 hn623257 658128 816b 41c464 hn62324 M7202A
Contextual Info: MEM ORY ICs FUNCTION GUIDE 3. C R O S S REFERENCE GUIDE 3.1 DRAM Density Org. Samsung Mode Toshiba Hitachi Fujitsu H M 51 256 M B 81256 NEC Oki 64K X 1 Page K M 416 4 25 6 K X 1 F. Page KM 41C256 TC 51256 Nibble KM 41C257 TC51257 S. C olu m n KM 41C258 TC 51258

Contextual Info: LH540201/02 PRELIMINARY CMOS 512 x 9 /1 0 2 4 x 9 A syn ch ro n o u s FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540201/02 is a FIFO First-In, First-Out mem­ ory device, based on fully-static CMOS dual-port SRAM