LVCH16272 Search Results

LVCH16272

Abstract: SN74 SN74ALVCH16272 A5-13
Contextual Info: SN74A LVCH16272 12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS S C E S 0 S 7 - O C TO B E R 1995 description This 12-bit to 24-bit bus exchanger is designed for 2.3-V to 3.3-V V q c operation. The LVCH16272 is intended for applica­ tions where two separate datapaths must be

IDT74LVCH162721A

Abstract: LVCH162721A SO56-2
Contextual Info: LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP ADVANCE WITH 3-STATE OUTPUTS, INFORMATION 5 VOLT TOLERANT I/O, BUS-HOLD Integrated Device Technology, Inc. DESCRIPTION: FEATURES: This 20-bit flip-flop is built using advanced dual metal CMOS technology. The 20 flip-flops of the LVCH162721A are edgetriggered D-type flip-flops with qualified clock storage. On the

74LVC05

Abstract: 7400 datasheet 2-input nand gate 74LVC05A LVC1G04 transistor x1 pv 25 inverter board design pv 74ALVC1G04 74ALVCH244 7400 nand gate series 74ALVC1G14
Contextual Info: Selector Guide for ALVC/LVC Products the leading provider of high-performance logic. From single-gate to 32-bit, IDT is your source for ALVC/LVC logic. Today’s designers are developing the most challenging telecommunications, networking and PC products ever designed

Contextual Info: LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP ADVANCE WITH 3-STATE OUTPUTS, INFORMATION 5 VOLT TOLERANT I/O, BUS-HOLD FEATURES: - Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.635mm pitch SSOP, 0.50mm pitch TSSOP

Contextual Info: LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP ADVANCE WITH 3-STATE OUTPUTS, INFORMATION 5 VOLT TOLERANT I/O, BUS-HOLD FEATURES: - Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.635mm pitch SSOP, 0.50mm pitch TSSOP

IDT74LVCH162721A

Abstract: LVCH162721A
Contextual Info: LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION: FEATURES: This 20-bit flip-flop is built using advanced dual metal CMOS technology.

H 721A

Contextual Info: LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION: FEATURES: This 20-bit flip-flop is built using advanced dual metal CMOS technology.

721a

Abstract: IDT74LVCH162721A LVCH162721A SO56-2
Contextual Info: LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD FEATURES: – – – – – – – – – DESCRIPTION:

block diagram of mri machine

Abstract: IDT74LVCH162721A LVCH162721A
Contextual Info: LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD FEATURES: - Typical tsK o (Output Skew) < 250ps - ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) - 0.635mm pitch SSOP, 0.50mm pitch TSSOP

Contextual Info: LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD FEATURES: – – – – – – – – – DESCRIPTION:

SO56-1

Contextual Info: LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE LVCH162721A 3.3V CMOS 20-BIT ADVANCE FLIP-FLOP WITH 3-STATE INFORMATION OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD FEATURES: – – – – – –