ORGATE Search Results

glc556

Abstract: G4736 lg controller circuit diagram OR-GATES Lg Prime 3b game controller chip prime 3b
Contextual Info: @ LG Semicon. Co. LTD. Description Pin Configuration GLC560 is an integrated chip of two timers, two ORgates, control signal buffers and game data buffers. It can support one game controller without any additional TTL devices. Thus, it offers simple solution to the Super I/O card. Game port logic

lvc32a

Abstract: orgate IDT74LVC32A
Contextual Info: IDT74LVC32A 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE WITH 5 VOLT TOLERANT I/O D E S C R IP TIO N FEATURES: - 0.5 MICRON CMOS Technology - ESD > 2000V per MlL-STD-883, Method 3015; - The LVC32A quadruple 2-input positive -ORgate is built using advanced

DF2-A

Abstract: XB2H DF2E
Contextual Info: TL3M Device Triple Level 3 Mapper TXC-03453 DESCRIPTION • Maps up to three independent DS3/E3 line formats into SDH/SONET formats as follows: - DS3 to/from STM-1/TUG-3 - DS3 to/from STS-3/STS-1 - E3 to/from STM-1/TUG-3 • SDH/SONET bus access: - Byte wide drop and add buses

rneg2

Contextual Info: QT1F-Plus Device Quad T1 Framer-Plus TXC-03103C DESCRIPTION • D4 SF, ESF including HDLC Link support , and transparent framing modes • Encodes/decodes AMI/B8ZS and forced ones density line codes • Fractional T1 gapped clock • Monitor function for frame pulse, clock and data

TH4B

Contextual Info: PHAST-3N STM-1/STS-3/STS-3c SDH/SONET Overhead Terminator with Telecom Bus Interface TXC-06103 DATA SHEET • • • • • • • • • • • • • • • • • Bit-serial SDH/SONET line interface - Pseudo-ECL interface with clock recovery and synthesis

Contextual Info: LM2744 www.ti.com SNVS292F – SEPTEMBER 2004 – REVISED MARCH 2013 LM2744 Low Voltage N-Channel MOSFET Synchronous Buck Regulator Controller with External Reference Check for Samples: LM2744 FEATURES DESCRIPTION • • • • • The LM2744 is a high-speed synchronous buck

dual opamp 4560

Abstract: OF560
Contextual Info: LM2747 Synchronous Buck Controller with Pre-bias Startup, and Optional Clock Synchronization General Description Features The LM2747 is a high-speed synchronous buck regulator controller with a feedback voltage accuracy of ±1%. It can provide simple down conversion to output voltages as low as

buck boost converter closed loop in matlab

Abstract: APC powerwise
Contextual Info: LM10520 LM10520 Single-Phase Buck Controller for AVS Systems Literature Number: SNVS638 LM10520 Single-Phase Buck Controller for AVS Systems General Description Key Specifications The LM10520 is a single-phase Energy Management Unit EMU that actively reduces system-level power consumption

74AUP1G126

Abstract: 74AUP1G32 JESD22-A114E 74AUP1T1326
Contextual Info: 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state Rev. 01 — 20 January 2009 Product data sheet 1. General description The 74AUP1T1326 is a high-performance, low-power, low-voltage, single-bit, dual supply buffer/line driver with output enable circuitry.

27s25

Abstract: AM27S25 am9517 ck 6112 Z8000
Contextual Info: Am6112 12-Bit High-Speed ADC INTRODUCTION OPERATION The Am 6112 is a m onolithic m icroprocessor com patible 12-bit high-speed Analog-to-Digital Converter ADC . A typical conversion tim e ot 6 us allows its use in applica­ tions previously requiring much m ore costly m ultichip

Contextual Info: Tiva TM4C123G Development Board User's Guide Literature Number: SPMU357B August 2013 – Revised March 2014 Contents 1 DK-TM4C123G Overview 1.1 1.2 1.3 1.4 2 Hardware Description 2.1 2.2 2.3 2.4 2.5 3 . 4

X009

Abstract: MGAB A10 fbnl MGAB
Contextual Info: TEMx28 Device 21/28 Channel Dual Bus High Density Mapper TXC-04222 DESCRIPTION • Add/drop up to 28 E1, DS1, or VT/TU payloads from two add and two drop STM-1/VC4, STS-3 buses • Add bus and drop bus timing modes • Cross mapping applications DS1 mapped to/from

ASI4U Application Notes

Abstract: asi bus SAP5 Evaluation Board 2.0 1N4001 1N4148 BZV55C39 SSOP28 TEMD5000 zmd programmer ZMD cross reference
Contextual Info: ASI4U Universal Actuator-Sensor Interface IC Datasheet Features • • • • • • • • • • • Description ASI4U is a monolithic CMOS integrated circuit certified for AS-i Actuator Sensor Interface networks. AS-i networks are used for industrial

transistor bl p89

Abstract: bl p74 transistor J955 XC4000 XC4000A XC4000D XC4000E XC4000EX XC4000H p180 g8
Contextual Info: book XC4000E and XC4000X Series Field Programmable Gate Arrays R January 29, 1999 Version 1.5 6* XC4000E and XC4000X Series Features Note: XC4000 Series devices described in this data sheet include the XC4000E family and XC4000X Series. XC4000X Series devices described in this data sheet

n117

Contextual Info: DS3F Device DS3 Framer TXC-03401B DATA SHEET • DS3 payload access, bit-serial or nibble-parallel • C-bit parity or M13 operating mode • C-bit interface 13 C-bits in, 14 out • Detect and generate DS3 AIS, and idle signals • Transmit reference generator for serial operation

X6777

Abstract: X6705 XC4000 XC4000E XC4000EX XC4000X XC4000XL Signal Path Designer
Contextual Info: APPLICATION NOTE  XAPP 056 November 6, 1997 Version 1.2 System Design with New XC4000X I/O Features Application Note by Lois Cartier Summary The XC4000X FPGA family provides several new I/O features, including an additional latch on each input and an output

4076B

Abstract: 4000B
Contextual Info: 4076B INTERNATIONAL, INC. CMOS 4-BIT D-TYPE REGISTER FEATURES ♦ 3-State Outputs with Gated Control Lines ♦ Fully Independent Clock ♦ Asynchronous Reset ♦ Fully Static Operation • DC to 12MHz @ lOVdc DESCRIPTION The 4076B 4-bit Register consists of

GAL16VB

Abstract: National SEMICONDUCTOR GAL16V8 GAL16V8 application notes GAL16v8 algorithm
Contextual Info: GAL16V8 National Semiconductor GAL16V8 Generic Array Logic General Description Features The NSC E2CMOS GAL device combines a high per­ formance CMOS process with electrically erasable floating gate technology. This programmable memory technology applied to array logic provides designers with reconfigurable

GAL Gate Array Logic

Abstract: GAL20V6
Contextual Info: GAL20V8 3 National Semiconductor GAL20V8 Generic Array Logic General Description The NSC E^CMOStm GAL device combines a high per­ formance CMOS process with electrically erasable floating gate technology. This programmable memory technology applied to array logic provides designers with reconfigurable

8251 uart

Abstract: SERIAL CONTROLLER 8251 VNS80000 vlsi vlsi cmos circuitry VNS8000 UART 8251 VLSI Solution implement codec G.711 8251 programmable communication interface
Contextual Info: Networking Communications VIP Single-Chip VLSI ISDN Subscriber Processor OVERVIEW F E AT U R E S The VLSI ISDN Subscriber Processor VIP offers in a single device a powerful programmable engine for ISDN subscriber communications. It includes most of the circuitry

PPO100

Abstract: PPO107 PPO112 SPC700 CXP871P40 tuner vcr
Contextual Info: CXP871P40 CMOS 8-bit Single Chip Microcomputer Description The CXP871P40 is a CMOS 8-bit microcomputer which consists of A/D converter, serial interface 2ch independently , timer/counter, time base timer, vector interruption, high precision timing pattern

sealectro

Abstract: interfacing ADC with 8086 microprocessor AD7880 AD7880BN AD7880BQ AD7880CN DB10 50-007-0000 ic2 7493 pin
Contextual Info: a FEATURES 12-Bit Monolithic A/D Converter 66 kHz Throughput Rate 12 ␮s Conversion Time 3 ␮s On-Chip Track/Hold Amplifier Low Power Power Save Mode: 2 mW typ Normal Operation: 25 mW typ 70 dB SNR Fast Data Access Time: 57 ns Small 24-Lead SOIC and 0.3" DIP Packages

7.3*4.3*2.8mm

Abstract: VJ1206A102 VJ1206A102k LM2727 LM2737 MTC14 Si4826DY SLF12575T-1R2N8R2 TDK MLCC 1206 100uF LM27x7
Contextual Info: LM2727/LM2737 N-Channel FET Synchronous Buck Regulator Controller for Low Output Voltages General Description Features The LM2727 and LM2737 are high-speed, synchronous, switching regulator controllers. They are intended to control currents of 0.7A to 20A with up to 95% conversion efficiencies. The LM2727 employs output over-voltage and undervoltage latch-off. For applications where latch-off is not desired, the LM2737 can be used. Power up and down

digital phase detector

Abstract: Phase Frequency detector 74AC11074 TC9122 TLC2932 TLC2932IPW TC9122 p Transistor w2n
Contextual Info: TLC2932 Phase-Locked-Loop Building Block With Analog Voltage-Controlled Oscillator and Phase Frequency Detector SLAA011A August 1996 Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and