P 7473 N Search Results

450024

Abstract: 4511 ZH705 5-1D-95 1d06
Contextual Info: L— DME REV ECN B -2Ä-C H XQ - - 8 -S -Ö 4 X1 Ö51D TRW 1 -11 -05 AO 6661 TRM 5 -1 0 -0 $ BO 7I2B JAF 5-12-Q Ä B1 7131 JAF 1 -3 0 -0 6 BZ 7473 JM P A R T NUMBER , m [11 ] — - 4 5 0 -0 2 3 APPTX. #Y COLOR YELLOW 4 5 0 -0 2 4 CLEAR 4 5 0 -0 2 5 BLACK 45D-Q 2G

Contextual Info: L— DAT REV ECN B -2 5 -0 4 XQ - - 8 -6 -0 4 X1 Ö51D TRW 1 -11 -05 AO BG6I TRM 5-1 C H E BO 7120 JAF 5 -1 2 -0 4 B1 7131 JAF 1-3D -D 6 BZ 7473 M P A R T NUMBER , m [11 ] — - 4 5 0 -0 2 3 V. tJÏÏDÜF J i l l APPTX9Y COLOR YELLOW 45 1-02 4 CLEAR 4 5 0 -0 2 5

pin diagram of 7473

Abstract: ttl 7473 N74LS73 7473 pin diagram 74LS73 ok2t p 7473 n 74LS73 TTL 7473 Flip-Flops 7473
Contextual Info: 7473, LS73 Signetics Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '73 is a dual flip-flop with individual J, K, C lock and direct Reset inputs. The 7473 is positive pulse-triggered. JK infor­ mation is loaded into the m aster while

IC 7473

Abstract: pin diagram for IC 7473 circuit diagram for IC 7473 pin DIAGRAM OF IC 7473 IC 74LS73 7473 pin diagram ic 7473 pin diagram Flip-Flop 7473 7473 equivalent pin configuration of IC 7473
Contextual Info: 7473, LS73 Signetics Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '73 is a dual flip-flop with individual J, K, Clock and direct Reset inputs. The 7473 is positive pulse-triggered. JK infor­ mation is loaded into the master while

7476 truth table

Abstract: 7474 truth table fairchild 9322 se 9315-1 signetics 8281 7474 equivalent 9N73/7473 82S62 signetics 8235 93178
Contextual Info: SELECTOR GUIDE/FUNCTIONAL INDEX MSI MULTIPLEXERS Function Type No. Enable Input Comple­ mentary O u tp ut 9322 93L22 Dual 4 -Input 9309 93L09 93153 X X X X Single 8 -In p u t 9312 93L12 93S12 9313 93151 93152 X X X X X X 93150 X X X X X X X Page No. Data Z

F7473

Abstract: C0203
Contextual Info: OfUVIN» MUE JN THJM0 AMtLt MQJECTfQN THIS DRAWING 15 U N P U 0 L I SHED. @ comiaMT i» LOC RELEASED FOR PUBLICATION ,19 IWaWWATÖ. AU. IM n»ur|«M AL AIONTS « S D M D . Ah TT AMP otar 50 p F IM E r— c - rV n 0.51 u 6.35C. 2503 2\ TIN PLATE 0.002032

WL 33

Abstract: ic 7473
Contextual Info: BY AMP ° ,19 INCORPORATED.ALL RIGHTS RESERVED. C c C O PY RI GH T 19 RE LEASED FOR PUBL IC AT IO N h IS UNPUBLISHED. r o THIS D R A W I N G DIST — tV 1— R E V I SI ON S æ w P LTR c D DWN APVD M. Y T. f DATE REVISED J-10649 REDRAWN WITHOUT CHANGE FJ00-0723-99

TTL 74139

Abstract: 74153 mux MSI 74148 16cudslr CI 74138 sn 74373 8mcomp 7404 7408 7432 7408, 7404, 7486, 7432 Flip-Flop 7471
Contextual Info: PLSLIB-TTL /$ ^ n^ X LIBRARY • TTL MacroFunction Library Diskette. • ADLIB, Altera Design Librarian Diskette. To increase design ease and productivity Altera has created M acroFunctions. These are high level building blocks that allow the user to design at

TTL 74ls74

Abstract: 74ls74 CI 7473 TTL 7474 7476 JK ttl 7474 14 PIN Jk 7476 7474 PIN DIAGRAM pin diagram 7474 7474 16 PIN
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED D55 9020 D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 5 ui 9 D UJ -=pi (3 J Q 2 — J SD 0 CP Z o (3 4 K Ä Co “LT in > </> O a 3 -0 K Co ° I- 3 a. I- 3 O 4-0 Co ? 15 D61 54/7474, 54H/74H74,

7473 dual JK

Abstract: 74109 74109 dual JK LS 7474
Contextual Info: — Dual JK-FFs w ith Preset and Clear 74109 V çç 9 1— 2 CLR 2J 2R 2 CK ] - L I - L CL" a 1J i n 20 J 1 — 1 20 PR j a L »CK ? CLR 1 r 2 PR I I I I i n A m t i J i i r w IK 1 CK 1 PR 10 1Q GND CLR O P O S, 0 7 4 7 4 $ -i Y L \ Z L t z 9 4 7 O f 1 7 0 -/7

Contextual Info: SLR -50L SILONEXI SER IES NPN S I L I C O N PLANAR E P I T A X I A L PHOTODARLINGTON General D e scrip tio n The S i l o n e x S L R - 5 0 L NPN s i l i c o n p l a n a r p h o t o d a r l i n g t o n s e r i e s i s mount ed i n a T O - 1 8 h i g h p r o f i l e lensed h erm etid ally s e a le d package.

7473 JK flip flop

Abstract: IC 74LS73 74LS73D 7473PC 74LS73 dual JK JK flip flop IC Flip-Flop 7473PC pin DIAGRAM OF IC 7473 74LS73 JK JK flip flop IC diagram
Contextual Info: 73 CO NNECTIO N DIAGRAM PINOUT A •A /Â 54/7473 ^ /54H /74H 73 O f1014 I/54LS/74LS73 DUAL JK FLIP-FLOP With Separate Clears and Clocks) D E S C R IP TIO N — The ’73 and ’H73 dual JK master/slave flip -flop s have a separate clock fo r each flip -flop . Inputs to the master section are controlled

54l73

Abstract: IC TTL 7473 SN54L73 IC 7473
Contextual Info: TYPES SN5473, SN54H73, SN54L73, SN54LS73A, SN7473, SN74H73, SN74LS73A DUAL J-K FLIP-FLOPS WITH CLEAR REVISED DECEMBER 1983 Package Options Include Plastic and C eram ic DIPs S N 5 4 L 7 3 . , . J P AC KA G E S N 7 4 7 3 , S N 7 4 H 7 3 . . . J OR N P AC K A G E

7404 dip

Abstract: 7493 4 bit binary counter 4 nand dip 16 74122 Retriggerable Monostable Multivibrator Noise immunity of 7408 7476 counter CI 7405 Noise immunity of 7486 decade counter 7492 7492 binary counter
Contextual Info: BIPOLAR DIGITAL ICs continued TYPE T T L - T 7 4 , T 54 series" z o 1Q. C TJ a. 5 B O- OC O I=3 O z < ÜJ ID < u < Q- C/3 LU O Gates T 7400/5400 Quad 2-input N A N D 10 40 10 D IP H,P T 7401/5401 Quad 2-input open-collector N A N D 10 40 10 D IP H,P T 7402/5402

MS25036-149

Abstract: MS25036 MS25036 weight M7928
Contextual Info: 4 DRAWING HADE IN THIRD ANGLE PROJECTION T H IS DRAWING IS U N P U B L IS H E D . RELEASED BY AMP C COPYRIGHT 19 FOR P U B L IC A T IO N INCORPORATED. LOC ,1 9 DIST G 14 ALL INTERNATIONAL RIGHTS RESERVED. R E V IS IO N S P F ZONE LTR DESCRIPTION y REV /

ic 7483 BCD adder

Abstract: 9N01 ic 7483 full adder IC 7490 pin configuration function of ic 7490 9N03 7401 ic configuration TIC 8213 pin configuration of ic 7492 Fairchild 9311
Contextual Info: SELECTOR GUIDE/FUNCTIONAL INDEX MSI ARITHMETIC OPERATORS ADDERS, A.L.U.'S, COMPARATORS, MULTIPLIERS Type No. Function Number of Bits Description t pd Power Dissipation Page No ns mW A d d itio n 9380 9304 93H183 9382 9383 Single 1-B it Full Adder Dual 1-B it Full Adder

STR W 5453 A

Abstract: STR 5453 STR W 5453 STR W 5453 C Truth Table 74190 Truth Table 74192 74193 truth table truth table 7454 str w c 5453 Truth Table 74193
Contextual Info: TTL/MSI 9393/5493, 7493 4 -B IT BINARY COUNTER D E S C R IP T IO N -T h e T T L /M S I 9393/5 4 9 3 , 7493 is a 4-Bit Binary Counter consisting of four master/ slave flip-flops which are internally interconnected to provide a divide-by-two counter and a divide-by-eight counter. A gated direct reset line is provided which inhibits the count inputs and

ci 74174

Abstract: ci 74273 74174 74175 74273
Contextual Info: — 74273 187 — Octal D-FFs VCC 80 r~ f ^ i — 80 — 70 r*i—r^i 70 60 — — L [j 3 0— 1 t r O 74749 “ • f 10 10 A7\ 0 3 i / 7 D ' 2D - CLOCK ~ r , Q CLEAR SO of—1 io —1 M d o— b CK* > » <»CK CLEAR I CLEAR I r-^ 7 f c“ SO — o 1—

CI 7473

Abstract: counter with 7473 7490 Decade Counter 7476 up down counter 7476 counter ci 74192 decade counter 7492 74122 Retriggerable Monostable Multivibrator ci 7476 7490 counter
Contextual Info: BIPOLAR DIGITAL ICs continued :lip-flops T 7472/5472 T 7473/5473 T 7474/5474 T 7476/5476 T 74107/54107 T 74121/54121 T 74122/54122 T 74123/54123 Jther functions T 7441 A/5441 A T 7442/5442 T 7443/5443 T 7444/5444 T 7475/5475 T 7481/5481 T 7483/5483 T 7484/5484

TTL 74ls74

Abstract: 7474 14 PIN 74ls76 7476 ttl ttl 74ls109 74LS107 74LS73 74ls74 TTL 74ls76 74LS109
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL M A S T E R /S LA V E E D G E -T R IG G E R E D D55 9020 D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 ui 9 D UJ 5 -=pi J Q (3 CP o K Z 2 — J SD 0 _6 Co (3 “LT in > z o Q J CP I- 3 a. 3 O So J - Ö K 4-0

FZH115B

Abstract: fzh261 FZK105 FZH131 FZJ111 FZH115 FZH205 Multiplexer IC 74151 FZH265B 74LS104
Contextual Info: Digital I.C.s, 74INTEGRATED CIRCUITS DIGITAL TTL, 74LS & 74HC Series Quad 2-input NAND gate Quad 2-input NAND gate, open collector Quad 2-input NOR gate Quad 2-input NOR gate, open collector Hex inverter Hex inverter, O/C collector Hex inverter, Buffer 30V O/P

7408 CMOS

Abstract: TTL 7452 ttl 74183 LS 74141 7408, 7404, 7486, 7432 7404 7408 7432 TTL 74289 74106 CMOS 4017 series ttl 74395
Contextual Info: KG10000 SERIES SEMI-CUSTOM CMOS GATE ARRAY CMOS SILOCON GATE ARRAY Th e KG10000 S e rie s is c o n sists o f s ilico n gate C M O S arrays w hose inte rco n n e ctio n are in itia lly u n s p e c ifie d , th e re fo re custom LSI is p ro ce sse d w ith o n ly one m ask ste p a cu sto m ize d m etal m ask a c c o rd ­

pin diagram for IC 7473

Abstract: 7473PC ic 7473 pin diagram of 7473 pin DIAGRAM OF IC 7473 7473 pin diagram Flip-Flop 7473PC 74LS73 dual JK IC 74LS73 74LS73DC
Contextual Info: 73 CONNECTION DIAGRAM PIN O U T A 54/7473 ^ , 54H /74H 73 o/IOti/ 1/54LS/74LS73 &/ / i ’ /3 DUAL JK FLIP-FLOP With Separate Clears and Clocks DESCRIPTION — The ’73 and ’H73 dual J K master/slave flip-flops have a separate clock for each flip-flop. Inputs to the master section are controlled

7473N

Abstract: circuit diagram for IC 7473 pin diagram for IC 7473 circuit diagram for DM 7473 ic 7473N 5473J DM54A 5473D
Contextual Info: I R C H I L D S E M I C O N D U C T O R TM DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs be allowed to change w hile th e clock is high. Data transfers to the outputs on the falling edge of th e clock pulse. A low logic level on th e clear input w ill reset the outputs regardless