PASIC380 Search Results

vhdl code for time division multiplexer

Abstract: vhdl projects abstract and coding radix delta ap 796n Controller C384 vhdl code for multiplexer SIGNAL PATH designer vhdl code for time division multiplexer abstract
Contextual Info: Designing with FPGAs t An Introduction to Cypress's pASIC380 Family Warp3 of FPGAs and the Design Tool simulation, and device specifics required in the deĆ Introduction sign description are discussed. Field Programmable Gate Arrays FPGA borrow the sea of gates concept from the gate array semicusĆ

programmer manual EPLD cypress

Abstract: pASIC380 programming manual EPLD CY7C383A GAL programmer schematic
Contextual Info: filename: Tuesday, August 11, 1992 Revision: October 9, 1995 pASIC380 Family UltraLogict Very High Speed CMOS FPGAs D Robust routing resources Features D Very high speed D D D D D D D Ċ Loadable counter frequencies greater than 150 MHz Ċ ChipĆtoĆchip operating frequencies

application of programmable array logic

Abstract: 4000 CMOS CMOS 4000 digital clock using logic gates FLASH370 pASIC380
Contextual Info: PRESS RELEASE CYPRESS EXPANDS FPGA OFFERING WITH 8,000-GATE DEVICES Highest Performance FPGAs Offer Full PCI Compliance For All Speed Grades SAN JOSE, Calif., February 27, 1995 - Cypress Semiconductor Corporation today introduced 8000-gate versions of its speed-leading pASIC380 family of fieldprogrammable gate arrays. The new CY7C387A and CY7C388A FPGAs are fully

programmer manual EPLD cypress

Contextual Info: l l lt fM d l l l t? . I U t? 5 U d y , M U y U 5 > l I I , ItKfcS Revision: Tuesday, June 28,1994 pASIC380 Family F/ CYPRESS Features • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz

pasic380

Abstract: Cypress Semiconductor CY3125 CY3146 synopsys
Contextual Info: CY3146: April 19, 1995 Revision: September 14, 1995 PRELIMINARY Features CY3146 Synopsys Design Software Kit for pASIC380t Ordering Information CY3146 Synopsys pASIC380 FPGA Design Software SunĆbased includes: 3½Ćinch disk Sun version pASIC FPGA Synopsys Library

CY7C381P

Abstract: CY7C381P-0JC CY7C381P-XJC CY7C381P-XJI CY7C382P CY7C383A CY7C385P 100-Pin CPGA Package Pin-Out Diagram
Contextual Info: CY7C381P CY7C382P CYPRESS Features • Very high speed — Loadable counter frequencies greater than 150 MHz — Chip-to-chip operating frequencies up to 110 MHz — Input + logic cell + output delays under 6 ns • Unparalleled FPGA performance for counters, data path, state machines,

CY7C3381A

Abstract: CY7C3381A-0JC CY7C3381A-0JI CY7C3381A-XJC CY7C3382A CY7C3384A CY7C3385A 00252-B
Contextual Info: CY7C3381A CY7C3382A CYPRESS Features • Very high speed — Loadable counter frequencies greater than SO MHz — Chip-to-chip operating frequencies up to 60 MHz • Unparalleled FPGA performance for counters, data path, state machines, arithmetic, and random logic

frws 5-4

Abstract: CY7C381-0JI C3816 G68 Package vhdl code for lte channel coding CY7C381 CY7C382 7c381 C381-9 C3812
Contextual Info: ¡iiö i id in tJ . iv iu iiu c iy , M u y u t ji i / , Revision: Wednesday, March 16,1994 ¥ CY7C381 CY7C382 cypress Features • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz — Input + logic cell + output delays

Contextual Info: tvjooim. iviunuay, oepiariiuei ¿u, i»»o Revision: Tuesday, May 10,1994 r# CYPRESS Features • Very high speed — Loadable counter frequencies greater than 150 MHz — Chip-to-chip operating frequencies up to 120 MHz — Input + logic cell + output delays

kt 84l

Contextual Info: CY7C385P CY7C386P » r CYPR ESS UltraLogic Very High Speed 4K Gate CMOS FPGA Features • Very high speed — Loadable counter frequencies greater than 150 MHz — Chip-to-chip operating frequencies up to 110 MHz — Input + logic cell + output delays under 6 ns

Contextual Info: Revision: Thursday, September 24,1992 MUR 23 1993 PRELIMINARY CYPRESS s7-W '" SEMICONDUCTOR Features • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz — Input + logic cell + output delays

Contextual Info: CY7C3381A CY7C3382A 5r CYPRESS Features • Very high speed — Loadable counter frequencies greater than SO MHz — Chip-to-chip operating frequencies up to 60 MHz UltraLogic 3.3V High Speed IK Gate CMOS FPGA — PC and workstation platforms Functional Description

Contextual Info: PRELIMINARY CYPRESS SEMICONDUCTOR Very High Speed 2K 6K Gate CMOS FPGA — Waveform simulation with back annotated net delays — PC and workstation platforms • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies

Contextual Info: Revision: Monday, December 14,1992 a* CY7C381 CY7C382 PRELIMINARY H v p p rc c — Very High Speed IK 3K Gate CMOS FPGA SEMICONDUCTOR Features • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies

architecture of cypress FLASH370 device

Abstract: FLASH370
Contextual Info: PRESS RELEASE CYPRESS ADDS NEW SYNTHESIS CAPABILITY, FPGA SUPPORT TO $99 WARP2 Leading VHDL Programming Tool Now Supports All Cypress PLDs, CPLDs, and FPGAs SAN JOSE, Calif., April 22, 1996 - Cypress Semiconductor Corp. today introduced Release 4 of its highly popular, $99 VHDL-based Warp2

for full adder and half adder

Abstract: datasheet for full adder and half adder carry save adder 16-bit adder pasic380 half adder transistor h9 16 bit adder 16 bit full adder applications of half adder
Contextual Info: DESIGN TIPS Carry-Save Addition Saves Logic, Time Summing multiple operands is a common operation for signal processing applications. One such application requires summing eight, 16-bit operands to generate a 19-bit result. Pipelining is required to achieve the system’s required

fifo

Abstract: ofwe CY7C384A addr RDCO CY7C4245 RT 8214 RT 8206 tag 8206
Contextual Info: Interfacing to RACEway: PitCREWjr D Used to interface between FIFOs and the General RACEway protocol. D Drives/receives a RACEway port directly. D Simple PitCREWjr is a simple fullĆduplex onĆramp to the RACEway fabric. The device has a standard RACEĆ master

CY7C384A

Abstract: CY7C383A-1JC CY7C383A-1JI CY7C383A-2JC CY7C383A-2JI CY7C383A
Contextual Info: filename:Monday, August 10, 1992 Revision: October 5, 1995 CY7C383A CY7C384A UltraLogict Very High Speed 2K Gate CMOS FPGA Features D Very high speed D D D D D Ċ Loadable counter frequencies greater than 150 MHz Ċ ChipĆtoĆchip operating frequencies up to 110 MHz

CC186

Abstract: CY7C3387P-1AI CY7C3387P-0AC CY7C3387P-0AI CY7C3387P-1AC
Contextual Info: 7c3387a/8a: March 2, 1995 Revision: October 6, 1995 PRELIMINARY UltraLogict Very High Speed 8K Gate CMOS FPGA Ċ 16Ćbit counter operating at 80 MHz Features D Very high speed Ċ Loadable counter frequencies greater than 80 MHz Ċ ChipĆtoĆchip operating frequencies

CY7C3383A-0JC

Abstract: CY7C3383A-1JC CY7C3383A-1JI
Contextual Info: CY7C3383A: January 4, 1995 Revision: October 9, 1995 CY7C3383A CY7C3384A UltraLogict 3.3V High Speed 2K Gate CMOS FPGA Features D Very high speed D D D D D D Functional Description Ċ See Development Systems section D 5V tolerant Inputs see IIH spec D Robust routing resources

CY7C385P-2AC

Abstract: CY7C385P-2AI CY7C385P-2JC
Contextual Info: filename:Monday, June 15, 1992 Revision: October 9, 1995 CY7C385P CY7C386P UltraLogict Very High Speed 4K Gate CMOS FPGA Features D Very high speed D D D D D D Ċ Loadable counter frequencies greater than 150 MHz Ċ ChipĆtoĆchip operating frequencies up to 110 MHz

n20s

Abstract: pasic380 A144 CY7C3386A CY7C3387P CY7C3388P
Contextual Info: PRELIMINARY 5f CYPRESS Features • Very high speed — Loadable counter frequencies greater than 80 MHz — Chip-to-chip operating frequencies up to 60 MHz • Unparalleled FPGA performance for counters, data path, state machines, arithm etic, and random logic

architecture of cypress FLASH370 device

Abstract: architecture of cypress FLASH370 cpld FLASH370
Contextual Info: PRESS RELEASE CYPRESS CPLDs ADD IN-SYSTEM REPROGRAMMABILITY FLASH370i Devices Also Offer PCI Compliance, Bus-Hold Feature SAN JOSE, Calif., July 15, 1996 - Taking advantage of the outstanding routability and fixed timing model of its FLASH370 family of complex programmable logic devices

for full adder and half adder

Abstract: carry save adder for half adder applications of half adder
Contextual Info: Cypress OnLine Vol 2/#2 11/12/96 9:33 AM Page 3 1,1 DESIGN TIPS Carry-Save Addition Saves Logic, Time Summing multiple operands is a common operation for signal processing applications. One such application requires summing eight, 16-bit operands to generate a 19-bit result. Pipelining is