RECONFIG Search Results

Contextual Info: TLV1562 2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN SLAS162 – SEPTEMBER 1998 D D D D D D D D D D D 2 MSPS Max Throughput at 10 Bit Single Channel , ±1 LSB DNL, ±1 LSB INL MAX

93LC46B CIRCUIT DIAGRAM

Abstract: TRAC-S2Q16 93LC46B AN27 QSOP16 ZSM560 NM92C46
Contextual Info: TRAC SUPPORT CIRCUIT TRAC-S2 ISSUE 1 - JANUARY 2000 DEVICE DESCRIPTION The TRAC family of Field Programmable Analog Devices offers an integrated path from signal processing problems to working silicon solutions - in minutes! The Totally Reconfigurable Analog Circuit is a highly

20V8Q

Abstract: SL06 20V8H-15 20V8 GAL20V8 PAL20R8 PALCE20V8 PD3024 pal20v8
Contextual Info: COM'L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25, Q-20/25 PALCE20V8 Family EE CMOS 24-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS ◆ Pin and function compatible with all PAL 20V8 devices ◆ Electrically erasable CMOS technology provides reconfigurable logic and full testability

AC307

Abstract: SPARTAN 3E STARTER BOARD L262144 memory 2114 XILINX/SPARTAN 3E STARTER BOARD AFS090 generic SPI AFS-EVAL
Contextual Info: Application Note AC307 Configuring SRAM FPGAs Using Actel Fusion Introduction Due to the nature of SRAM technology, SRAM-based FPGAs are volatile and lose their configuration when powered off, so they must be reconfigured at every power-up. Hence, almost every system using SRAMbased FPGAs contains an additional nonvolatile memory, such as flash PROM or EEPROM, to store the

intel embedded microcontroller handbook

Abstract: RG-11/U COM20020 COM20020D CQM20020 RG62 COM20020B
Contextual Info: COM20020D PRELIMINARY STANDARD MICROSYSTEMS CORPORATION COM20020 ULANC Revision D Universal Local Area Network Controller with 2K X 8 On-Board RAM FEATURES • • • • • • • • • • • New Features for Rev. D • Data Rates up to 5 Mbps Programmable Reconfiguration Times

XRP7740

Abstract: XRP-7740 Digital Proportional Controller
Contextual Info: Product Number: XRP7740EVB Evaluation Board for XRP-7740 - Programmable Power System ICs Reduce Development Time, Cost and are Easily Reconfigured for Real-time Design Changes Exar has released the XRP7740, a 5Amp/channel regulator. These power ICs integrate the best of both worlds - the low cost and flexibility of digital power

Contextual Info: DWG NO. SH C -4 9 5 -5 1 0 0 -5 0 0 REV ZO N E C.MURPHY 26874 ADDED DATUMS AND POS TOL R.C 0 3 /0 8 /9 9 K.LEBLANC 30404 COMPLETE RECONFIGURE: SEE SCR LL 3 /2 4 / 0 0 K.LEBLANC 32005 ADDED NOTE 7, SEE SCR SG 9 /1 8 / 0 0 K.LEBLANC 33150 ADDED NOTE 8 SG 1/2 /0 1

BD 4908 fm

Abstract: BD 4908 ch126a
Contextual Info: TLV1562 2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN SLAS16 2 -S E P T E M B E R 1998 2 MSPS Max Throughput at 10 Bit Single Channel , ±1 LSB DNL, ±1 LSB INL MAX

Contextual Info: IC S 24 9 4 IC S 24 9 4 A Integrated Circuit Systems, Inc. Dual Video/Memory Clock Generator Features New Features • • • • • • • • • • • World standard ICS2494A has been reconfigured to allow 8 memory frequencies. Mask-programmable frequencies

75176B

Abstract: COM20019I COM20019I-HD COM20019ILJP COM20020
Contextual Info: COM20019I Low Cost ARCNET ANSI 878.1 Controller with 2K x 8 On-Board RAM Datasheet Product Features Eight, 256 Byte Pages Allow Four Pages TX and RX Plus Scratch-Pad Memory New Features: − Data Rates up to 312.5 Kbps − Programmable Reconfiguration Times

Contextual Info: Dynamic Reconfiguration in Stratix V Devices 6 2013.05.06 SV52008 Subscribe Feedback The transceiver reconfiguration controller offers several different dynamic reconfiguration modes. You can choose the appropriate reconfiguration mode that best suits your application needs. All the dynamic

Contextual Info: Reconfiguration Timings for AnadigmApex VDD RESETb ERRb goes low if missing or corrupt inverse sync byte detected ERRb Open Drain Continuous clock max freq = 40MHz ACLK Reconfiguration start Reconfiguration end Reconfiguration becomes active if in automatic

TR54016

Abstract: XRT86L38 XRT86VL34 XRT86VL34IB PIN26
Contextual Info: XRT86VL34 QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION JANUARY 2007 REV. V1.2.0 GENERAL DESCRIPTION The XRT86VL34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .

USB2524

Abstract: 56-PIN QFN-56 USB2524-ABZJ 4 port usb2.0 hub
Contextual Info: USB2524 USB MultiSwitchTM Hub PRODUCT FEATURES „ Datasheet USB2.0 Compatible 4-Port Hub with two upstream host port connections „ — Provides electronic reconfiguration and re-assignment of any of its 4 downstream ports to either of two upstream host ports “on-the-fly” .

teradyne tester test system

Abstract: Z1800 teradyne XC9500
Contextual Info: Integrating XC9500 ISP Capabilities With Manufacturing Test on the Teradyne Z1800 I n-system programming ISP allows you to program and re-program devices that are already soldered on a system board. ISP streamlines manufacturing flows, allows you to update and reconfigure remote systems,

flip-flop 948

Abstract: 5252 f 1101 SN74AS8840 CNTR11-CNTR8 Zeus Component AS8832
Contextual Info: SN74AS8840. Digital Crossbar Switch • High-speed programmable switch for parallel processing applications • Dynam ically reconfigurable for fault-tolerant routing • 64 bidirectional data I/O s in 16 nibble four-bit groups • D ata I/O selection programmable by nibble

GAL16VB

Abstract: National SEMICONDUCTOR GAL16V8 GAL16V8 application notes GAL16v8 algorithm
Contextual Info: GAL16V8 National Semiconductor GAL16V8 Generic Array Logic General Description Features The NSC E2CMOS GAL device combines a high per­ formance CMOS process with electrically erasable floating gate technology. This programmable memory technology applied to array logic provides designers with reconfigurable

GAL Gate Array Logic

Abstract: GAL20V6
Contextual Info: GAL20V8 3 National Semiconductor GAL20V8 Generic Array Logic General Description The NSC E^CMOStm GAL device combines a high per­ formance CMOS process with electrically erasable floating gate technology. This programmable memory technology applied to array logic provides designers with reconfigurable

XAPP879

Abstract: UG382 Spartan-6 FPGA DCM_CLKGEN
Contextual Info: Application Note: Spartan-6 Family PLL Dynamic Reconfiguration Author: Karl Kurbjun and Carl Ribbing XAPP879 v1.0 May 13, 2010 Summary This application note provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the Spartan -6 FPGA Phase Locked Loop (PLL) through its

DMO 565 R

Abstract: dmo 465 Twelve NC Code
Contextual Info: xr XRT86L34 PRELIMINARY QUAD T1/E1/J1 FRAMER/LIU COMBO NOVEMBER 2004 REV. P1.1.6 GENERAL DESCRIPTION The XRT86L34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .

chn 923

Contextual Info: xr XRT75R03 THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR MARCH 2005 REV. 1.0.7 GENERAL DESCRIPTION TRANSMITTER: The XRT75R03 is a three-channel fully integrated Line Interface Unit LIU featuring EXAR’s R3 Technology (Reconfigurable, Relayless Redundancy)

zero crossing detector

Abstract: zero crossing TAN20-1 TRAC United Detector silicon mer capacitor PRICE
Contextual Info: TRAC Application Note AN20 Issue 1 November 1998 Zero Crossing Detector Utilising TRAC Ian Shaw The TRAC family of totally reconfigurable Field Programmable Analog Devices offers an integrated path from signal processing problems t o w o r k i n g s i l i c o n s o l u t io n s - in

IPAC-X - PSB 21150

Abstract: ISAC-SX - PEB 3086 Reconfigurable PBX PEB 3086 F PSB 21150 F IOM-2 Handler PSB 21150 F 1.4 PEB 3086 H C161 DD11
Contextual Info: Application Note, DS1, April 2001 Reconfigurable PBX IPAC-X PSB 21150, ISAC-SX PEB 3086, ISAC-SX TE PSB 3186 & SBCX-X PEB 3081 Wi r ed Communications N e v e r s t o p t h i n k i n g . Edition 2001-04-06 Published by Infineon Technologies AG, St.-Martin-Strasse 53,

hid lamp controller

Abstract: AN10 TL5001 Analog Solutions FZT789 zetex fzt789
Contextual Info: TRAC Application Note AN10 Issue 1 September 1998 Constant Power Delivery Utilising TRAC Kambiz Pourhady The TRAC family of totally reconfigurable Field Programmable Analog Devices offers an integrated path from signal processing problems t o w o r k i n g s i l i c o n s o l u t ions - i n