SCAA056 Search Results

SCAA056

Abstract: 325R1 SLLA067 CDC111 CDCVF111 SLLA101 SN65LVDS32 SN65LVDS33 SN65LVDT33
Contextual Info: Application Report SCAA056 –December 2001 Interfacing Between LVPECL, LVDS, and CML High Performance Analog/CDC Kal Mustafa ABSTRACT This application note describes various methods of interfacing between different logic levels. It focuses on interconnection between LVPECL low voltage positive-referenced

Contextual Info: CDCVF111 1:9 DIFFERENTIAL LVPECL CLOCK DRIVER SCAS670B – SEPTEMBER 2001 – REVISED JUNE 2002 D Low-Output Skew for Clock-Distribution FN PACKAGE TOP VIEW Applications D D (LVPECL) Compatible Inputs and Outputs Distributes Differential Clock Inputs to Nine

c.i 9409

Contextual Info: CDC339 CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS331 – DECEMBER 1992 – REVISED MARCH 1994 D D D D D D D DB OR DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and Outputs Distributes One Clock Input to Eight

CDCLVP110

Abstract: CDCLVP110MVFR LVEP111 MC100 PTN1111 SCAA056
Contextual Info: CDCLVP110 www.ti.com SCAS683D – JUNE 2002 – REVISED JANUARY 2011 Low-Voltage 1:10 LVPECL/HSTL With Selectable Input Clock Driver Check for Samples: CDCLVP110 FEATURES 1 • • • • • • • • • Distributes One Differential Clock Input Pair LVPECL/HSTL to 10 Differential LVPECL Clock

CDCLVP110

Abstract: LVEP111 MC100 PTN1111 SCAA056 S-PQFP-G32 scas683
Contextual Info: CDCLVP110 LOW-VOLTAGE 1:10 LVPECL/HSTL WITH SELECTABLE INPUT CLOCK DRIVER SCAS683 A– JUNE 2002 – REVISED AUGUST 2002 D Distributes One Differential Clock Input D D D D D D D Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 Pair LVPECL/HSTL to Ten Differential LVPECL Clock Outputs

Contextual Info: CDCV850, CDCV850I 2.5ĆV PHASE LOCK LOOP CLOCK DRIVER WITH 2ĆLINE SERIAL INTERFACE SCAS647B – OCTOBER 2000 – REVISED DECEMBER 2002 D Phase-Lock Loop Clock Driver for Double D D D D D D D D D Data-Rate Synchronous DRAM Applications Spread Spectrum Clock Compatible

cdclvp111vf

Abstract: CDCLVP111 CDCLVP111RHBR LVEP111 MC100 PTN1111 QFN32 SCAA056
Contextual Info: CDCLVP111 www.ti.com SCAS859C – JANUARY 2009 – REVISED NOVEMBER 2009 LOW-VOLTAGE 1:10 LVPECL WITH SELECTABLE INPUT CLOCK DRIVER Check for Samples :CDCLVP111 FEATURES APPLICATIONS • • • 1 2 • • • • • • • • Distributes One Differential Clock Input Pair

Contextual Info: CDC857-2, CDC857-3 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS SCAS627A – SEPTEMBER 1999 – DECEMBER 1999 D D D D D D Phase-Lock Loop Clock Distribution for Double Data Rate Synchronous DRAM Applications Distributes One Differential Clock Input to Ten Differential Outputs

Contextual Info: CDCV857B 2.5-V PHASE LOCK LOOP CLOCK DRIVER SCAS676 – JUNE 2002 D Phase-Lock Loop Clock Driver for Double D D D D D description GND Y0 Y0 VDDQ Y1 Y1 GND GND Y2 Y2 VDDQ VDDQ CLK CLK VDDQ AVDD AGND GND Y3 Y3 VDDQ Y4 Y4 GND 1 48 2 47 3 46 4 45 5 44 6 43 7 42

CDCLVP110

Abstract: CDCLVP110VF LVEP111 MC100 PTN1111 SCAA056
Contextual Info: CDCLVP110 www.ti.com SCAS683A – JUNE 2002 – REVISED AUGUST 2002 LOW-VOLTAGE 1:10 LVPECL/HSTL WITH SELECTABLE INPUT CLOCK DRIVER FEATURES • • • • • • • • • DESCRIPTION Distributes One Differential Clock Input Pair LVPECL/HSTL to 10 Differential LVPECL

SN65LVDS100 Application Report

Abstract: CDC111 CDCLVP110 CDCVF111 SN65LVDS101 SN65LVDT100 SN65LVDT33 SLLA101 sn65lvds CML100
Contextual Info: Application Report SCAA059C – March 2003 – Revised October 2007 AC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML Kal Mustafa/Chris Sterzik. High Performance Analog

Contextual Info: CDCLVP110 www.ti.com SCAS683A – JUNE 2002 – REVISED AUGUST 2002 LOW-VOLTAGE 1:10 LVPECL/HSTL WITH SELECTABLE INPUT CLOCK DRIVER FEATURES • • • • • • • • • DESCRIPTION Distributes One Differential Clock Input Pair LVPECL/HSTL to 10 Differential LVPECL

INSSTE32882

Abstract: maxim dallas 2501 P16CV SY100EL16 SN65MLVD201 SN65EPT22 INCU877 INCUA877 ttl crystal oscillator using 7404 P16CV857B
Contextual Info: Clocks and Timing Guide www.ti.com/clocks 2Q 2009 2 Clocks and Timing Guide ➔ Clocks and Timing Selection Tree Clocks by Function Clock Distribution Non- PLL Fanout Buffers PLL Buffers RF Synthesizers Clock Generation General Purpose Generator/Synthesizer

Contextual Info: CDCLVP110 www.ti.com SCAS683D – JUNE 2002 – REVISED JANUARY 2011 Low-Voltage 1:10 LVPECL/HSTL With Selectable Input Clock Driver Check for Samples: CDCLVP110 FEATURES 1 • • • • • • • • • Distributes One Differential Clock Input Pair LVPECL/HSTL to 10 Differential LVPECL Clock

Contextual Info: CDCVF111 1:9 DIFFERENTIAL LVPECL CLOCK DRIVER SCAS670B – SEPTEMBER 2001 – REVISED JUNE 2002 D Low-Output Skew for Clock-Distribution FN PACKAGE TOP VIEW Applications D D (LVPECL) Compatible Inputs and Outputs Distributes Differential Clock Inputs to Nine

PC133 registered reference design

Contextual Info: CDCF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS628C – APRIL 1999 – REVISED MARCH 2001 D D D D D D D D D D D D D PW PACKAGE TOP VIEW Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9 Spread Spectrum Clock Compatible Operating Frequency 25 MHz to 140 MHz

Contextual Info: CDCLVP111 www.ti.com . SCAS859 – JANUARY 2009 LOW-VOLTAGE 1:10 LVPECL

MUX21

Contextual Info: CDC7005 3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER SCAS685A – DECEMBER 2002 – REVISED FEBRUARY 2003 D High Performance 1:5 PLL Clock TERMINAL ASSIGNMENTS TOP VIEW Synchronizer D Two Clock Inputs: VCXO_IN Clock Is D D D D D D D D D D

DALLAS 2501

Abstract: CDC2509 TSSOP-56 footprint texas 14 pin ic 7404 datasheet SN65MLVD201 pll dip 546 spi mux CDCVF25084 TTL 7404 TBA 950 2x
Contextual Info: R E A L W O R L D S I G N A L P TM R O C E S S I N G Clocks and Timing Selection Guide 4Q 2003 Table of Contents Overview Clock Distribution Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

CDCVF111

Abstract: MS-018 SCAA055 SCAA056
Contextual Info: CDCVF111 1:9 DIFFERENTIAL LVPECL CLOCK DRIVER SCAS670B – SEPTEMBER 2001 – REVISED JUNE 2002 D Low-Output Skew for Clock-Distribution FN PACKAGE TOP VIEW Applications D D (LVPECL) Compatible Inputs and Outputs Distributes Differential Clock Inputs to Nine

Contextual Info: CDCVF111 1:9 DIFFERENTIAL LVPECL CLOCK DRIVER SCAS670B – SEPTEMBER 2001 – REVISED JUNE 2002 D Low-Output Skew for Clock-Distribution FN PACKAGE TOP VIEW Applications D D (LVPECL) Compatible Inputs and Outputs Distributes Differential Clock Inputs to Nine

Contextual Info: CDCVF25081 3.3-V PHASED-LOCK LOOP CLOCK DRIVER SCAS671 – OCTOBER 2001 D Phase-Locked Loop-Based Zero-Delay D PACKAGE SOIC PW PACKAGE (TSSOP) (TOP VIEW) Buffer D Operating Frequency: 10 MHz to 200 MHz D Low Jitter (Cycle-Cycle): ±100 ps Over the D D D

Contextual Info: CDC950 133ĆMHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS SCAS646A – FEBRUARY 2001 – REVISED SEPTEMBER 2001 D Generates Clocks for Next Generation D D D D D D D Microprocessors Uses a 14.318-MHz Crystal Input to Generate Multiple Output Frequencies

Contextual Info: CDCLVP215 www.ti.com SCAS853B – APRIL 2008 – REVISED NOVEMBER 2009 LOW-VOLTAGE DUAL DIFFERENTIAL 1:5 LVPECL CLOCK DRIVER Check for Samples: CDCLVP215 FEATURES 1 • • • • APPLICATIONS • • QA3 QA4 QA4 QB0 QB0 QB1 QB1 QA3 24 23 22 21 20 19 18 17