SI D 03 K Search Results

rigid cable

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schematic GSM ESD

Abstract: USIM card interface SIMCARD Schematic PROFET IEC-7816 usim cemi data mipi PCB layout WLP-8-11
Contextual Info: B GF1 06c Hipac SI M Ca rd Inte rfac e E MI Filte r and ES D Pr ot ection Applic atio n N ote A N 243 Revision: Rev. 1.1 2011-03-20 RF and P r otecti on D evic es Edition 2011-03-20 Published by Infineon Technologies AG

Contextual Info: 03 H A R R HS-82C85RH IS S E M I C O N D U C T O R D ecem ber 1992 Radiation Hardened CMOS Static Clock Controller/Generator Pinout Features • Radiation Hardened - Total Dose > 1 0s RAD Si - Transient Upset > 10s RAD(Siys - Latch U p Free EPI-CMOS - Functional A fter Total Dose 1 x 10s RAD(SI)

Contextual Info: Alle Rechte aorbehallen/ All rights reserved 5 U 2 3 1 Pr i n t e d boord l ayout , component si de pre assembled assembIed B Dal. Deloil. A 16-SEP-03 Noma SH Insp. Stand. 09181U9421 port number 31541 16-SEP-03 SH Mod. Dot. Nome HARTING EURL F -95972 Par i s

6J5P

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Contextual Info: Si PIN Photodiodes 4 Type No. Dimensional Outline (P.40-43)/ Window Material*' S1223 S1223 01 S3071 S3072 S1863-01 S3883 S3399 S5106 S5107 S3590 01 S3590 03 S3590 05 S3588 03 *1 W i n d o w m aterial, O /K K /K © /K ® /K ® /K ® /R ® /R Short Photo Sensitivity S (A/W) Typ.

Contextual Info: Mle Rechte aorbeballen/ All rights reserved 3 Pr i n t e d board l ayout , component si de LO LO r E±U f 1.8 pre assembled assembled B Dal. Deloil. A 16-SEP-03 Noma SH Insp. Stand. 09181409421 par t number 31541 16-SEP-03 SH Mod. Dot. Nome HARTING EURL F -95972 Par i s

74LV373

Abstract: 74HC573 74HCT573 74LV573 74LV573D 74LV573DB 74LV573N 74LV573PW JESD22-A114E
Contextual Info: 74LV573 Octal D-type transparent latch; 3-state Rev. 03 — 15 April 2009 Product data sheet 1. General description The 74LV573 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC573 and 74HCT573. The 74LV573 consists of eight D-type transparent latches, featuring separate D-type

Contextual Info: tile techie vorbelullen/ i l l rights resertei 5 2 3 U Deloil. Ool. M -NVK 20-JAN-03 S .H . Insp. Slond. 09560008275 0 . 7 6 jum Au 09560008277 3 Port number Performance level 31376 20-JAN-03 S .H . Nod. Dol. Noae HARTING EURL F-95972 Paris 1 D - S u b , h i g h den si l y ,

Contextual Info: Mle Rechte aorbeballen/ A ll rights reserved U 5 2 3 1 Pr i n t e d board l ayout , component si de 43. 40 ‘ 0.38 pre assembled assembIed O O CO n - l c c 1 t ^ 14x2, 54=35, 56 2, 54 - Deloil. 16-SEP-03 SH Dot. Nome 6.1 max 16-SEP-03 Noma MoDslob/ SH

74LVC544A

Abstract: 74LVC544AD 74LVC544ADB 74LVC544APW SO24 SSOP24 TSSOP24
Contextual Info: 74LVC544A Octal D-type registered transceiver; inverting; 3-state Rev. 03 — 11 May 2004 Product data sheet 1. General description The 74LVC544A is a high-performance, low-power, low-voltage, Si-gate CMOS device superior to most advanced CMOS compatible TTL families.

Contextual Info: 74LVC544A Octal D-type registered transceiver; inverting; 3-state Rev. 03 — 11 May 2004 Product data sheet 1. General description The 74LVC544A is a high-performance, low-power, low-voltage, Si-gate CMOS device superior to most advanced CMOS compatible TTL families.

74HC573

Abstract: 74HC_HCT573 74HC573 20 PIN Current 74HCT573 74HC573 Logic Package Information 74HC573N 74HC573 Datasheet 74HC573-74HCT573 74HC573D 74HCT573D
Contextual Info: 74HC573; 74HCT573 Octal D-type transparent latch; 3-state Rev. 03 — 17 January 2006 Product data sheet 1. General description The 74HC573; 74HCT573 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . The 74HC573; 74HCT573 has octal D-type transparent latches featuring separate D-type

74HC273

Abstract: HCT273 74HC273N TSSOP20 Package 74HCT273 SO20 Package SSOP20 package 74HC273BQ 74HC273D 74HC273DB
Contextual Info: 74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger Rev. 03 — 24 January 2006 Product data sheet 1. General description The 74HC273; 74HCT273 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL .

Contextual Info: Technical Data CD54/74HC534, CD54/74HCT534 CD54/74HC564, CD54/74HCT564 File N um ber 1640 High-Speed CMOS Logic Do — D ,— — Oo Di — — Q1 - Q j Octal D-Type Flip-Flop, 3-State, Inverting 03 — — as Positive-Edge Triggered — — Qi — Si 04

Contextual Info: HMXADC9225 Radiation Hardened 12-Bit, 20 MSPS Monolithic A/D Converter Features           PRODUCTION - Release - 09 Jul 2014 03:13:41 MST - Printed on 18 Jul 2014  Monolithic 12-Bit, 20 MSPS A/D Converter Rad Hard: 500k Rad Si Total Dose

Contextual Info: SI-07 Te c E R M 8 -03 0 -S -D -E M 2-L E R M 8-060-L-D -E M 2 ER M 8-025-S -D -E M 2-D S EDGE MOUNT EDGE RATE SPECIFICATIONS ERM8-EM SERIES Mates with: ERF8 For complete specifications and recommended PCB layouts see www.samtec.com?ERM8-EM Insulator Material:

MNA423

Abstract: 74LV74
Contextual Info: 74LV74 Dual D-type flip-flop with set and reset; positive edge-trigger Rev. 03 — 28 September 2007 Product data sheet 1. General description The 74LV74 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC74 and 74HCT74. The device is a dual positive edge triggered D-type flip-flop with individual data D inputs,

1-569-19MA9

Abstract: Ka-59-438-m06 ka-59-438 KA-59
Contextual Info: GSD .05 D. .03 3 HOLES REVISIONS CHANGES CN 36690 A REDRAWN ME 11/13/95 I Cn CO I 4^ O si OO I S o œ STAMP: KINGS KA-59-438-M06 NOTES: 1. FOR USE WITH RC-142 AND 223 CABLE GROUPS. 2. FOR CABLING INSTRUCTIONS SEE CP-465. 3. FOR CRIMPING USE DIE KTH-2061.

Contextual Info: 4 THIS DRAWING IS C O P Y R IG H T 3 U N P U B L IS H E D . 19 RELEASED BY AMP FOR ALL IN COR PO RA TE D. PUBLICATION RIGHTS 2 , 19 LOC RE SE R VE D . REVI SI ONS DI ST FT 69 L TR DESCRIPTION RE V PER DATE 0G3C-0156-03 30CT04 DWN APVD JR MZ D D FINISH:

74hc373

Abstract: 74HC373N 74HCT373 data sheet SSOP20 74HC373 74HC373 So20 74HCT373 74HCT373N 74HC533 74HC563 74HC573
Contextual Info: 74HC373; 74HCT373 Octal D-type transparent latch; 3-state Rev. 03 — 20 January 2006 Product data sheet 1. General description The 74HC373; 74HCT373 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.

74AHC573

Abstract: 74AHC573D 74AHCT373 74AHCT573 74AHC373 74AHCT563
Contextual Info: 74AHC573; 74AHCT573 Octal D-type transparant latch; 3-state Rev. 03 — 24 April 2008 Product data sheet 1. General description The 74AHC573; 74AHCT573 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . It is specified in compliance with JEDEC standard

AHCT373

Contextual Info: 74AHC373; 74AHCT373 Octal D-type transparant latch; 3-state Rev. 03 — 20 May 2008 Product data sheet 1. General description The 74AHC373; 74AHCT373 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . It is specified in compliance with JEDEC standard

Contextual Info: THIS DRAWING IS UNPUBUSHED. COPYRIGHT RELEASED FOR PUBLICATION BY TYCO ELECTRONICS CORPORATION. LOC ALL RIGHTS RESERVED. AF Dl ST REVISIONS 50 LTR DESCRIPTION REV PER 0G 3A— 0 4 7 7 — 03 D 1 CONTINUOUS 2 MATING 3 WIRE 4 I NSULATI ON .21 O SI ZE THK