STP2014 Search Results

STP2014

Abstract: MK48T08-1 EBA11 STP2104 AmZ8 AD27 AD29 AD30
Contextual Info: STP2014.frm 1 Mon Jul 7 08:25:34 1997 STP2014 July 1997 SEC DATA SHEET SBus-to-EBus Controller DESCRIPTION The STP2014 SBus-to-EBus Controller SEC is an interface between the SBus and the EBus that is used for slow I/O devices such as TOD, EPROM, serial port, and keyboard/mouse. The STP2014 also houses the interrupt control and steering logic, the timer/counter registers, reset logic, and miscellaneous registers. The

Contextual Info: STP2014 S un M ic r o e l e c t r o n ic s July 1997 SEC DATA SHEET SBus-to-EBus Controller D e s c r ip t io n The STP2014 SBus-to-EBus Controller SEC is an interface between the SBus and the EBus that is used for slow I/O devices such as TOD, EPROM, serial port, and keyboard/mouse. The STP2014 also houses the inter­

STP2014QFP

Contextual Info: STP2014.frm 1 Mon Jul 7 08:25:34 1997 S un M e ic r o e l e c t r o n ic s J u ly 1997 SEC DATA SHEET SBus-to-EBus Controller D e s c r ip t io n The STP2014 SBus-to-EBus Controller SEC is an interface between the SBus and the EBus that is used for slow I/O devices such as TOD, EPROM, serial port, and keyboard/m ouse. The STP2014 also houses the inter­

E-BA8

Abstract: ISOS refer STP2104
Contextual Info: S un M ic ro electro nics July 1997 SEC DATA SHEET SBus-to-EBus Controller D e s c r ip t io n The STP2014 SBus-to-EBus Controller SEC is an interface between the SBus and the EBus that is used for slow I/O devices such as TOD, EPROM, serial port, and keyboard/mouse. The STP2014 also houses the inter­

lcd cross reference

Abstract: SME2411BGA SuperSPARC 805-0086-02 PMC cross reference STP2003QFP ATM622-S STP3010 STP2014QFP STP2024QFP
Contextual Info: S un M icroelectronics July 1997 Data Sheets listed by Product Name Cross Reference List Advanced PCI Bridge SME2411BGA ATM622-S SAR SME4050BGA 802-7894-02 Color LCD Controller STP3031 STP3031 Crossbar Switch XB1 STP2230SOP 802-7955-02 Dual System Controller

STP2012

Abstract: SuperSPARC STP2016QFP
Contextual Info: STP2016 S un M ic r o e l e c t r o n ic s J u ly 1997 Clock-2 Generator DATA SHEET System Clock Generator D e s c r ip t io n The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multiprocessing MP , operating at

STP2016

Abstract: SuperSPARC mbus 10 application STP2011 STP2016QFP mbus MCLK11 MOSC STP2012
Contextual Info: STP2016 July 1997 Clock-2 Generator System Clock Generator DATA SHEET DESCRIPTION The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multiprocessing MP , operating at

mbus 10 application

Abstract: STP2012 TP2018
Contextual Info: S un M icroelectronics July 1997 Clock-2 Generator DATA SHEET System Clock Generator D e s c r ip t io n The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multiprocessing

Contextual Info: S un M icro electro nics July 1997 MSBI DATA SHEET MBus to SBus Interface D e s c r ip t io n The STP2018 MBus to SBus Interface MSBI provides a bus bridge between two different busses used by a number of SPARC microprocessors and controls access to the I/O subsystem. The MBus is designed for

STP201

Contextual Info: SPA RC T echrdogy Business N ovem ber 1994 S T P 2016 DATA SHEET D C lo c k s G e n e ra to r escription The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multi­

53C90A

Abstract: ncr53c90 STP2012 53C90 AD12 AM7990 STP2013 EIRQ15 STP2011 53c90 scsi
Contextual Info: STP2012QFP July 1997 DMA2 DATA SHEET SBus DMA Controller DESCRIPTION The STP2012 SBus DMA Controller DMA2 provides three channels for DMA transfers over the SBus. It has three external interfaces designed to provide DMA access to one AMD Am7990 Local Area Network Controller for the Ethernet (LANCE), one NCR 53C90 SCSI controller (ESP), and one programmable Centronics-type parallel port. The

sba20

Abstract: mbus master circuit
Contextual Info: S un M icro electro nics July 1997 MSI DATA SHEET MBus-to-SBus Interface D e s c r ip t io n The STP2011 MBus-to-SBus Interface MSI provides an interface between the MBus and the SBus and con­ trols access to the 1 /O subsystem. The MSI consists of two main functional blocks: the Memory Subsystem

IS279

Abstract: mbus master circuit
Contextual Info: S T P 2 0 1 1 P G A -5 0 S un M ic r o e le c t r o n ic s July 1997 MSI DATA SHEET MBus-to-SBus Interface D e s c r ip t io n The STP2011 MBus-to-SBus Interface MSI provides an interface between the MBus and the SBus and controls access to the I/O subsystem. The MSI consists of two main functional blocks: the Memory Subsystem and the I/O Subsystem.

supersparc

Abstract: STP2003QFP STP3010PGA 805-0086-02 lcd cross reference STP2013 PMC cross reference STP3010 ATM622-S STP2024QFP
Contextual Info: S un M icroelectronics July 1997 Data Sheets listed by Marketing Part Cross Reference List M a r k e t in g P a r t 501-4126 Fast Frame Buffer 3D 802-7509-02 501-4127 Fast Frame Buffer (2D) 802-7509-02 SME1040BGA UltraSPARC-ll/ 300 MHz 805-0086-02 SME2411BGFA

mbus master circuit

Abstract: STP2011 MAD44 mbus 10 application three phase ESC circuit diagrams MAD50
Contextual Info: STP2011PGA-50 July 1997 MSI DATA SHEET MBus-to-SBus Interface DESCRIPTION The STP2011 MBus-to-SBus Interface MSI provides an interface between the MBus and the SBus and controls access to the I/O subsystem. The MSI consists of two main functional blocks: the Memory Subsystem and the I/O Subsystem.

STP2018TAB

Abstract: STP2018 m-bus
Contextual Info: STP2018 July 1997 MSBI MBus to SBus Interface DATA SHEET DESCRIPTION The STP2018 MBus to SBus Interface MSBI provides a bus bridge between two different busses used by a number of SPARC microprocessors and controls access to the I/O subsystem. The MBus is designed for multiprocessing (MP),

Contextual Info: STP2018 S un M ic r o e l e c t r o n ic s J u ly 1997 MSBI MBus to SBus Interface DATA SHEET D e s c r ip t io n The STP2018 M Bus to SBus Interface MSBI provides a bus bridge betw een two different busses used by a num ber of SPARC m icroprocessors and controls access to the I /O subsystem. The M Bus is designed for