UPA 1.1 Search Results

YV20

Contextual Info: S un M icroelectronics July 1997 _ U2S DATA SHEET UPA-to-SBus Interface D e s c r ip t io n The STP2220ABGA U 2 S d e v i c e bridges UPA- UltraSPARC Port Architecture to the SBus. U2S, is the primary connection between the UPA port (including UltraSPARC-1 processors and memory) and the SBus

PA15

Abstract: PA19 STP2001 STP2200ABGA STP2210QFP STP2220ABGA STP2230SOP
Contextual Info: Preliminary STP2220ABGA July 1997 U2S UPA-to-SBus Interface DATA SHEET DESCRIPTION The STP2220ABGA U2S [1] device bridges UPA- UltraSPARC Port Architecture to the SBus. U2S, is the primary connection between the UPA port (including UltraSPARC-I processors and memory) and the SBus

BY575

Abstract: 28BZ 8 PINS J-354W display 16119
Contextual Info: 501-4126 3D 501-4127 (2D) July 1997 FFB DATA SHEET High Performance UPA Based 24-bit Frame Buffer DESCRIPTION The Fast Frame Buffer (FFB) is a high performance UPA based 24-bit frame buffer with an integer rendering pipeline for use in demanding graphic applications. It is a UPA slave-only, non-cached, PIO graphics output

UltraSPARC ii

Abstract: PI-275 UltraSPARC IIIi
Contextual Info: S un M icroelectronics July 1997 FFB DATASHEET High Performance UPA Based 24-bit Frame Buffer D e s c r ip t io n The Fast Frame Buffer FFB is a high performance UPA based 24-bit frame buffer with an integer rendering pipeline for use in demanding graphic applications. It is a UPA slave-only, non-cached, PIO graphics output

AE21 ARRAY DIODE

Abstract: Sun UltraSparc T1 STP2223BGA ac10 stc AAD20
Contextual Info: STP2223BGA July 1997 U2P DATA SHEET UPA to PCI Interface DESCRIPTION The U2P * chip is the primary connection on an UltraSPARC CPU board between the UPA System Bus including UltraSPARC Processors and Memory and a PCI based I/O Subsystem. Its major functions are

Contextual Info: Preliminary STP2220ABGA S un M ic r o e l e c t r o n ic s J u ly 1997 U2S UPA-to-SBus Interface DATA SHEET D e s c r ip t io n The STP2220ABGA U2S ^ device bridges UPA- UltraSPARC Port Architecture to the SBus. U2S, is the prim ary connection betw een the UPA port (including UltraSPARC-1 processors and m em ory) and the SBus

upa64

Abstract: UPA128 STP221
Contextual Info: S un M icroelectronics July 1997 u se Uniprocessor System Controller DATA SHEET D e s c r ip t io n The Uniprocessor System Controller USC has a DRAM memory controller and functions to regulate the flow of requests and data on the UPA bus. It also controls the resets going to all UPA clients.

Contextual Info: STP2200ABGA S un M ic r o e l e c t r o n ic s July 1997 use Uniprocessor System Controller DATA SHEET D e s c r ip t io n The Uniprocessor System Controller USC has a DRAM m em ory controller and functions to regulate the flow of requests and data on the UPA bus. It also controls the resets going to all UPA clients.

circuit diagram video transmitter and receiver

Abstract: WIRING diagram hdmi to rca AL9M803B-EVB-A6 HDMI to RCA PLC Video Link module ir transmitter and receiver sensor av to HDMI Wireless Camera transmitter YPbPr to HDMI free av to hdmi circuit diagram
Contextual Info: Features ● Supports up to1920x1080@60i or 1920x1080@24p input sources ● H.264 compression technology ● Uses PLC for wireless streaming ● Supports different PLC technology including HomePlug-AV, HD-PLC, and UPA ● MPEG-1 layer II Stereo Audio supported, optional 5.1 channel

MCE-100

Abstract: STP1081 STP5211UPA-250 MC100LVE111 MC100LVE210
Contextual Info: STP5211 July 1997 UltraSPARC -II CPU Module DATA SHEET Complete 248 MHz CPU, 1.0 MB E-Cache, UDB-II DESCRIPTION The UltraSPARC-II module is a high performance, SPARC V9 compliant, small form factor processor module. It interfaces to the UltraSPARC Port Architecture UPA interconnect bus.

MCE-100

Abstract: MCE100
Contextual Info: STP5212 July 1997 UltraSPARC -II CPU Module DATA SHEET Complete 296 MHz CPU, 2.0 MB E-Cache, UDB-II DESCRIPTION The UltraSPARC-II module is a high performance, SPARC V9 compliant, small form factor processor module. It interfaces to the UltraSPARC Port Architecture UPA interconnect bus.

MCE-100

Abstract: ULTRASPARC-II stp1081 Sun UltraSparc MC100LVE111 MC100LVE210 STP5212UPA-300 SPARC v9 architecture BLOCK DIAGRAM Motherboard socket 754 BGA 328
Contextual Info: STP5212 July 1997 UltraSPARC -II CPU Module DATA SHEET Complete 296 MHz CPU, 2.0 MB E-Cache, UDB-II DESCRIPTION The UltraSPARC-II module is a high performance, SPARC V9 compliant, small form factor processor module. It interfaces to the UltraSPARC Port Architecture UPA interconnect bus.

64KX1

Contextual Info: STP5111A July 1997 UltraSPARC -I CPU Module DATA SHEET 200 MHz UltraSPARC-I + 1 MB E-Cache + UDBs DESCRIPTION The UltraSPARC-I module is a high performance, SPARC V9 compliant, small form factor processor module, which interfaces to the UltraSPARC Port Architecture UPA interconnect bus.

WIRING diagram hdmi to rca

Abstract: hdmi to rca plc wiring home diagram transmitter and receiver audio with 3.3v supply hdmi to 5.1 rca plc wiring diagram YPbPr to HDMI 1920x1080 ypbpr receiver plc module wiring diagram
Contextual Info: Features ● Supports up to1920x1080@60i or 1920x1080@24p input sources ● H.264 compression technology ● Uses PLC for wireless streaming ● Supports different PLC technology including HomePlug-AV, HD-PLC, and UPA ● MPEG-1 layer II Stereo Audio supported, optional 5.1 channel

W48C60

Abstract: w48c60-422 805-0086-02 SME1040 UltraSPARC ii J0801 tba 940 MC100LVEL39 MC12430 SME5421MCZ-300
Contextual Info: SME5421MCZ-300 July 1998 UltraSPARC -IIi CPU Module DATA SHEET 300 MHz CPU, 0.5 MB E-cache, UPA, 66 MHz PCI DESCRIPTION [1] The UltraSPARC™-IIi CPU module is a high performance, SPARC V9-compliant, small form-factor CPU module. It interfaces to the UltraSPARC Port Architecture 64S UPA64S interconnect bus, main memory, and

SRAM

Abstract: ultrasparc
Contextual Info: S un M icro electro nics July 1997 UltraSPARC ”-! CPU Module DATA SHEET 167 MHz UltraSPARC-1 + 0.5 MB E-Cache + UDBs D e s c r ip t io n The UltraSPARC-1 module is a high performance, SPARC V9 compliant, small form factor processor module, which interfaces to the UltraSPARC Port Architecture UPA interconnect bus.

48c60

Abstract: CZ-333
Contextual Info: SME5421MCZ-333 June 1998 m icrosystem s UltraSPARC-ll/ CPU Module DATA SHEET 333 MHz CPU, 2MB E-cache, UPA, 66 MHz PCI F u n c t io n a l D e s c r ip t io n [1] The UltraSPARC-IIi CPU M odule is a high perform ance, SPARC V9-com pliant, small form -factor processor

Contextual Info: S un M ic r o e l e c t r o n ic » Fast Frame Bu er High Performance UPA Based 24-bit Frame Buffer Preliminary Data Sheet J a n u a ry 19 97 501-4126 3D) 501-4127 (2D) microsystems Preliminary 5D1 -41 26 ( 3 D ) 5D1 -41 27 ( 2 D ) January 1997 FFB DATA SHEET

STP1081

Abstract: 75193 Sun UltraSparc T2 40N20
Contextual Info: STP1081 July 1997 UltraSPARC -II Data Buffer UDB-II DATA SHEET Companion Device for 250/300 MHz UltraSPARC-II Systems DESCRIPTION The UltraSPARC-II Data Buffer (UDB-II) consists of two identical ASICs connecting the UltraSPARC-II microprocessor and its E-Cache to the system data bus (i.e., UPA bus). These two are designated UDB_H (for the

W48C60

Abstract: J0801 w48c60-422 J0901 MC100LVEL39 MC12430 SME5410MCZ-270 587-pin TMS 3450 TMS 3450 specifications
Contextual Info: SME5410MCZ-270 July 1998 UltraSPARC -IIi CPU Module DATA SHEET 270 MHz CPU, 256 Kbyte E-cache, UPA, 66 MHz PCI DESCRIPTION The UltraSPARC™-IIi CPU module SME5410MCZ-270 is a high performance, SPARC V9-compliant, small form-factor CPU module. It interfaces to the UltraSPARC Port Architecture 64S (UPA64S) interconnect bus,

in138

Abstract: SPARC v9 architecture BLOCK DIAGRAM cpu lga UltraSPARC ii
Contextual Info: S un M icro electro nics July 1997 UltraSPARC -!! CPU Module DATA SHEET Complete 296 MHz CPU, 2.0 MB E-Cache, UDB-II D e s c r ip t io n The UltraSPARC-II module is a high performance, SPARC V9 compliant, small form factor processor module. It interfaces to the UltraSPARC Port Architecture UPA interconnect bus.

Contextual Info: SME541OMCZ-270 microsystems Ju ly 1998 UltraSPARC -ll/CPU Module DATA SHEET 270 M Hz CPU, 256 Kbyte E-cache, UPA, 66 M Hz PCI D e s c r ip t io n The UltraSPARC™ -IIi CPU m odule SME5410MCZ-270 is a high perform ance, SPARC™ V 9-com pliant, sm all

ultrasparc

Contextual Info: UltraSPARC “-!! Data Buffer UDB-II DATA SHEET Companion Device for 250/300 MHz UltraSPARC-II Systems D e s c r ip t io n The UltraSPARC-II Data Buffer (UDB-II) consists of two identical ASICs connecting the UltraSPARC-II micro­ processor and its E-Cache to the system data bus (i.e., UPA bus). These two are designated UDB_H (for the

805-0086-02

Abstract: J0801 UltraSPARC ii Sun UltraSparc II
Contextual Info: SME5421MCZ-300 microsystems Ju ly 1998 UltraSPARC -ll/CPU Module DATA SHEET 300 M Hz CPU, 0.5 MB E-cache, UPA, 66 M Hz PCI D e s c r ip tio n '11 The UltraSPARC™-Hi CPU m odule is a h igh perform ance, SPARC V9-com pliant, sm all form -factor CPU m odule. It interfaces to the UltraSPARC P ort A rchitecture 64S UPA64S interconnect bus, m ain m em ory, and