VDO CLOCK Search Results

Q2220

Abstract: Q2220I50N Q2220M-40L
Contextual Info: TECHNICAL SPECIFICATIONS Absolut« Maximum Ratings Q2220I-50 PARAMETER Q2220M-40L SYMBOL MIN MAX MIN MAX UNITS Storage Temperature Ts -40.0 +125.0 -65.0 +150.0 °C Operating Temperature Ta -40.0 +85.0 -55.0 +125.0 °c V dd -0.3 +7.0 -0.3 +7.0 V -0.3 VDo +0.3

fbii

Abstract: motherboard ga clock generator for 4040
Contextual Info: COMPUTING AND^NET WORKING Figure 1. Block Diagram VDO T1 CLKIN GA1210E FBIN EN2 INVI TO GND Clock Doubler/ Two-Phase Generator Features TriQuint's GA1210E is a low-skew TTL-level clock doubler chip. It produces multiple clock outputs, at precisely 2X the input frequency, which are all phase-aligned to a periodic clock

CD4060BMS

Abstract: IOH15
Contextual Info: S H" »® CD4060BMS D ecem ber 1992 CMOS 14 Stage Ripple-Carry Binary Counter/Divider and Oscillator Pinout Features • High Voltage Type 20V Rating • Common Reset • 12MHz Clock Rate at 1SV Q12 [ 7 Ü l VDO 013 [ ? ii| o io 014 Ü m ] q« • Fully Static Operation

Contextual Info: LC2M0S 12-Bit 1 u s ADC AD7586 ANALOG DEVICES □ FEATURES 1 us Conversion Time AGND and VREF Force/Sense Connections 12-Bit Monotonic over Temperature Low Power - 200 mW typ Fast Bus Access Time - <57 ns FUNCTIONAL BLOCK DIAGRAM vdo MODE C S RD CO NVST APPLICATIONS

Contextual Info: PICI 2C5XX M ic r o c h ip EPROM Memory Programming Specification This document includes the programming specifications for the following devices: Pin Diagram PDIP, SOIC, CW • PIC12C508 • PIC12C509 1.0 2 o IO O Ul VDO - GP5/OSC1/CLKIN • GP4/OSC2/CLKOUTGP3/RCCR/VPP-

40188

Abstract: 4072B 4521B 4727B 4022B 4045B 4029B 40178 4018B BCD counter
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-CMOS C83 4583B C84 40014B Rextna R extpa 5 (s ) (7 ) R extca He x t n b Vdd = Pin 16 Vss — Pin 8 0 = Pin Numbers C86 4075B C8S 4072B VDO r - C87 4073B V dd nc V dd i^innrnFirarTim I q a _ 0 1^1 LLlLillilLLlliJUJLJ

Contextual Info: CD4029A Types CMOS Presettable Up/Down Counter INPUTS Vdo Binary or BCD-Decade Features: • Medium speed operation . . . 5 M H z typ. @ C l =15 pF and V DD~ V SS- 1 0 V The RCA-C D 4029A consists o f a four-stage binary or BCD-decade up/dow n counter w ith

Contextual Info: GEC P L E S S E Y I S E M I C O N D U C T O R S~| DS3163-1.0 Supersedes C1080FDS Issue 2 MA8112 DIGITAL SWITCH MODULE DSM DIO [ 1 26 ] FSP1 DH [ 2 27 ] VdO 26 ] cuc DB [ 3 DO [ 4 25 ] Ct1 DI4 [ 5

4069B

Abstract: 4049B TTL LOGIC 4071B 4078B 4072B 4093B Level Translators 4069UB nor schmitt mos
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-CMOS C8 4078B C7 4002B V DD s — 11 2 3 4 NC Vo C10 4071B C9 4081B Vdo VDD L-a^ r^ -¿J UaL vss C12 4049B C11 4069B, 40014B rf>°~ NOTE: The Flatpak versions have the same pinouts Connection D iagram as the Dual In-Line Packages.

Contextual Info: H A R R CD40104BMS CD40194BMS I S S E M I C O N D U C T O R CMOS 4-Bit Bidirectional Universal Shift Register Decem ber 1992 Pinouts Features CD40104BMS TOP VIEW • High Voltage Type 20V Rating • Medium Speed fC L = 12MHz (typ.) a t V D D = 10V Ü] VDO

DS1277

Abstract: s1277
Contextual Info: DALLAS SEMICONDUCTOR DS1277 8-Channel Crosspoint Switch FEATURES PIN ASSIGNMENT • Any port A input/output can be programmed for con­ nection to any port B input/output CLK C 1 RSf C 2 ^ D/Q C 3 3 VDO 3 NC 22 3 +BAT PA1 C 4 21 D V |£ • All port input/output pins will accept both analog and

cd40138

Abstract: MC 140088 MC14025 cii 50 MC14001u schematic diagram of CD40138 mci4001 MC14001UB MC14002UB MC14011UB
Contextual Info: CMOS UB'SERIES GATES PIN A SSIG NM ENTS M C 14001U B Q u ad 2 -In p u t NOR G a te M C 14002U B D ual 4 -In p u t NOR G ata ' KJ" 1C= In 1A vDO =314 2 C= maA in 2ß =113 3C= OutA tO10 =112 4C= OutB OUtQ =111 sen In lg Outc =1 10 6= *n2B In 2q =3 9 7d VSS tn 1q =3 *

SMD MARKING q2 jp

Abstract: MC500 TQ1089-MC500 TQ1089-MC700 TQ1090 TQ1090-MC500 TQ1090-MC700 PS 307 10A 2pd12 18T marking
Contextual Info: R I r a Q U s I N S E M I C O N D U C T O R , I N C T i F ig u re 1. B lo c k D ia g ra m FBIN TQ1090 SI REFCLK SB rrri n n TEST VDD Q0 r n E E E r h GND GND GND r n m m 3 3 3 Phase Detector VCO a GND t Q1 Q2 VDD E E E VDO Q10 09 11-Output Configurable Clock Buffer

Contextual Info: 1 800 253-7007 R&E INTERNATIONAL. INC SCL4027B SCL4013B DUAL JK TYPE FU P FLOP DUAL D TYPE FUP FLOP Vpo o2 14 13 1 2 JT27 s2 | 12 c l 3 1 CL, 4 2 1 11 L r 2 d 1 10 5 1" Vdo 2 9 8 6 7 a i CL, « i K, Jl Si | 14 | | 12 | 13 11 | 10 1 9 5 1 *2 6 1 J2 7 1 s2

32KH2

Abstract: 3v timer 14pin
Contextual Info: 2. Product Lines 3*wire Serial Interlace ReaMime Clock IGs and Watchdog Timer RS5C317A/B Alarm, 32-kHz dock Output, The RS5C317A/B are 3-wire serial interface real-time clock ICs which differ only in the polarity of their serial clocks. In addition to the clock function,

Contextual Info: Preliminary WB1215 Serial Input PLL with 1.2GHz Prescaler Features Figure 1 Pin Diagram OSC_IN 1 20 ∅r NC 2 19 PWDN OSC_OUT 3 18 ∅p VP 4 17 Fout VCC 5 16 BISW DO 6 15 FC GND 7 14 LE LD 8 13 DATA NC 9 12 NC FIN 10 11 CLOCK • IC WORKS BiCMOS process • Operating voltage 2.7V to 5.5V

programmable counter ic

Contextual Info: Preliminary WB1225 Serial Input PLL with 2.5GHz Prescaler Features Figure 1 Pin Diagram OSC_IN 1 20 ∅r NC 2 19 PWDN OSC_OUT 3 18 ∅p VP 4 17 Fout VCC 5 16 BISW DO 6 15 FC GND 7 14 LE LD 8 13 DATA NC 9 12 NC FIN 10 11 CLOCK • IC WORKS BiCMOS process • Operating voltage 2.7V to 5.5V

Contextual Info: SYSTEM CLOCK CHIP IMISC415 CMOS LSI PLL FREQUENCY SYNTHESIZER December 1993 P R O D U C T FEA TURES • Generates All Essential Clock Signals for the Motherboards. ■ 4V to 7V Operating Supply Range. ■ Supports 80286-, 80386-, 80486-, and Pentium-Based Designs.

Contextual Info: Preliminary WB1220 Serial Input PLL with 2.0GHz Prescaler Features Figure 1 Pin Diagram OSC_IN 1 20 ∅r NC 2 19 PWDN OSC_OUT 3 18 ∅p VP 4 17 Fout VCC 5 16 BISW DO 6 15 FC GND 7 14 LE LD 8 13 DATA NC 9 12 NC FIN 10 11 CLOCK • IC WORKS BiCMOS process • Operating voltage 2.7V to 5.5V

Contextual Info: fD H A R R IS U S E M I C O N D U C T O R U CD4006BMS CMOS 18-Stage Static Register December 1992 Features • Pinout High-Voltage Type 20V Rating CD4006BM TOP VIEW • Fully Static Operation • Shifting Rates Up to 12MHz at 10V (typ) • Permanent Register Storage with Clock Una High or

STA090C3

Abstract: ix800
Contextual Info: SaRonix Crystal Clock Oscillator 3.3 voit, a c m o s , High Drive STA Series Technical Data Frequency Range: 250 kHz to 110 MHz Frequency Stability: ±25, ±50 or ±100 ppm over all conditions: calibration tolerance, operating temperature, input voltage change, load

Contextual Info: A S A H 1 KASE1 10 ^ [ A K 8424] AK8405 and CCD sensor timing signal generators, memory address and control signal generators, image processing circuitry, and a microprocessor interface.AK8424 can be also used with CIS Contact Image Sensor by additional small gates for modifing sensor clocks.

VDO 07 064 150

Contextual Info: CD4076BMS HARRIS S E M I C O N D U C T O R CMOS 4 -Bit D-Type Registers December 1992 Pinout Features CD4076BMS TOP VIEW • High Voltage Type 20V Rating • Three State Outputs • Input Disabled Without Gating the Clock OUTPUT DISABLE • Gated Output Control Lines for Enabling or Disabling

Contextual Info: I W D T IN/1X8327 I C M O TH ER B O A R D C L O C K G EN ERATO R FEATURES • C lock generator for PC/AT and PS/2 system • M ask program m able CPU clock up to 80 MHz • Provide seven clock outputs 14.318 MHz, 8/24/48 MHz, CPU clock, CPU clo ck/2 , 12X serial port