WF07580S Search Results

pin diagram priority encoder 74148

Abstract: priority encoder 16 to 4 74148 74148 PIN DIAGRAM pin diagram of 74148 priority encoder 74148 74148 pin diagram and function table 74148 74148 pin configuration pin diagram encoder 74148 encoder 74148
Contextual Info: 74148 Signetìcs Encoder 8-Input Priority Encoder Product Specification Logic Products FEATURES • • • • • • • • Code conversions Multi-channel D/A converter Decimal-to-BCD converter Cascading for priority encoding of "N" bits Input Enable capability

G3PS

Contextual Info: 74S182 Signetics Carry Generator Lookahead Carry Generator Product Specification Logic Products FEATURES • Provides carry lookahead across a group of four ALU's • Multi-level lookahead for high­ speed arithmetic operation over long word lengths TYPE TYPICAL PROPAGATION

TTL 7408

Abstract: TTL LS 7408 ls 7408 7408 AND GATE 3 input and gate 7408 7408 7408 TTL TTL 7408 AND propagation delay logic symbol 74LS08 74LS08 signetics
Contextual Info: Sjgnetìcs 7408, LS08, S08 Gates Quad Two-Input AND Gate Product Specification Logic Products TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT TOTAL 7408 15ns 16mA 74LS08 9ns 3.4mA 74S08 5ns 25mA ORDERING CODE COMMERCIAL RANGE Vcc = 5V ±5% ; T a = 0°C to + 70°C

1N3064

Abstract: 1N916 74LS 74S280 N74S280N S280 parity generator
Contextual Info: 74S280 Signetìcs Parity G enerator/C hecker 9-Bit Odd/Even Parity G enerator/Checker Product Specification Logic Products FEATURES • Buffered inputs — one normalized load • Word-length easily expanded by cascading • Similar pin configuration to '180

74156 demultiplexer

Abstract: 74LS156 equivalent TTL 74156 74156 74LS156 1N3064 demultiplexer 74ls 74LS LS156 N74LS156D
Contextual Info: 74156, LS156 Signetics Decoders/Demultiplexers Dual 2-Line To 4-Line Decoder/Demultiplexer Open Collector Product Specification Logic Products FEATURES • Common Address inputs • True or complement data demultiplexing • Dual 1-of-4 or 1-of-8 decoding

74ls gate symbols

Abstract: 74LS09 equal 74LS09 function table 74LS09 74LS logic gates 74LS09 N 74LS09 ttl 1N3064 1N916 74LS
Contextual Info: SigneHcs I 74LS09 I Gates Logic Products I Quad Two-Input AND Gate Open Collector f l Product Specification • TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 23 ns 4.3 74LS09 ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = 5 V ± 5% ; TA = 0°C to +70°C

74LS139

Abstract: 74l513 demultiplexer 74ls 74ls signetics pin diagram of 74LS 74LS 74S139 93L21 N74LS139D N74LS139N
Contextual Info: 74LS139, S139 Signetics Decoders/Demultiplexers Dual 1-of-4 D e c o d e r/D e m u ltip le x e r Product Specification Logic Products FEATURES • Demultiplexing capability • Two independent 1-of-4 decoders • Multifunction capability • Replaces 9321 and 93L21 for

74LS641

Abstract: 74LS641-1 74LS642 LS641 LS642 N74LS641-1N N74LS641N N74LS642N
Contextual Info: 74LS641, LS642, 74LS641-1, LS642-1 S ig n e lic s Transceivers Octal Bus Transceiver Open Collector Product Specification Logic Products FEATURES • Octal bidirectional bus interface • Open Collector Outputs — 'LS641, non-inverting — 'LS642, inverting

74LS245 buffer ic

Abstract: ic 74ls245 74LS245 74LS245 SIGNETICS 74LS245 interface function table of 74LS245 LS 74LS245
Contextual Info: Signetics 74 LS 2 45 Transceiver Octal Transceiver 3-State Product Specification Logic Products FEATURES • Octal bidirectional bus interface • 3-State buffer outputs TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 8ns 58 mA 74LS245 • PNP inputs for reduced loading

IC 7416

Abstract: f 7416 7416 TTL 7417 1/pcf 7416
Contextual Info: 7416, 17 Signetics Inverter/Buffer/Drivers '16 Hex Inverter B uffer/D river Open Collector '17 Hex B uffer/D river (Open Collector) Product Specification Logic Products TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 7416 10ns (tpLH) 15ns (tpHL)

I060S

Contextual Info: 74LS242, LS243, S242, S243 Signetics Transceivers '242 Quad Inverting Transceiver 3-State '243 Quad Transceiver (3-State) Logic Products Product Specification TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74LS242 FUNCTION TABLE, 242 OEb An

7421 pin configuration

Abstract: 7420 pin configuration 74LS20 PIN CONFIGURATION 7421 logic gate 7421 AND 74LS20 function table 74LS21 PIN CONFIGURATION TTL 7420 7421 AND gate PIN CONFIGURATION 7420
Contextual Info: Signehcs I 7420, 7421, LS20, LS21, S20 Gates Logic Products Dual Four-Input NAND '20 AND ('21) Gate Product Specification • TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7420 10ns 8mA 74LS20 10ns 0.8mA 8mA 74S20 3ns 7421 12ns 8mA 74LS21

F0758

Contextual Info: Signelics 174S135 Gate Quad Exclusive OR/NO R Gate Product Specification Logic Products TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT TOTAL 9ns 65 mA 74S135 FUNCTION TABLE INPUTS ORDERING CODE OUTPUT A B C Y L L H H L L H H L H L H L H L H L L L

Signetics BCD decoder

Abstract: ic ttl 74ls
Contextual Info: 74LS445 Signetìcs Decoder/Driver BCD-To-Decimal Decoder/Driver Open Collector Product Specification Logic Products FEATURES • • • • 80mA output drive capability 7V output breakdown voltage See '45 for 30V output voltage See '42 for standard TTL outputs

8T126

Abstract: 8T127 8T128 8T129 N8T126N N8T127N
Contextual Info: Signehcs 8T126, 127, 128, 129 Transceivers Quad, 3-State Transceivers Product Specification Logic Products DESCRIPTION The 8T126 and 8T128 feature a 3.4V minimum V oh level on the receiver for MOS interface applications. The send and receive buffers have separate En­

74ls gate symbols

Abstract: 74ls 74ls signetics 74LS136 N74LS136N 74ls Logic Family Specifications
Contextual Info: Signetics | 74LS136 G ate Quad T w o -In p u t Exclusive-O R Gate Open C o lle cto r Product Specification Logic P rod ucts TY PE T Y P IC A L P R O P A G A T IO N DELAY T Y P IC A L S U P P LY C U R R E N T (T O T A L ) 18ns 6.1m A 74L S 136 FUNCTION TABLE

IC 74156

Abstract: 74156 C005970S
Contextual Info: 74156, LS156 Signetics Decoders/Demultiplexers Dual 2-Line T o 4-Line D e c o d e r/D e m u ltip le x e r O pen C o llector Product Specification Logic Products FEATU RES • Common Address inputs • True or complement data demultiplexing • Dual l-of-4 or 1-of-8 decoding

74LS622

Abstract: ED 5BA
Contextual Info: 74 LS6 2 1 , LS622 Transceivers Signetics 'LS621 Non-Inverting Octal Bus Transceiver Open Collector 'LS622 Inverting Octal Bus Transceiver (Open Collector) Product Specification Logic Products FEATURES • Octal bidirectional bus interface • Open-collector output

Contextual Info: 74S280 Signetìcs Parity Generator/Checker 9-Bit O dd/Even Parity G enerator/Checker Product Specification Logic Products FEATURES • Buffered inputs — one normalized load • Word-length easily expanded by cascading • Similar pin configuration to '180

Contextual Info: 74S135 Signetics Gate Quad Exclusive OR/NOR Gate Product Specification Logic Products TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT TOTAL 9ns 65mA 74S135 FUNCTION TABLE INPUTS ORDERING CODE OUTPUT A B C Y L L H H L L H H L H L H L H L H L L L L H

74LS

Contextual Info: Signelics 74LS136 Gate Quad Two-Input Exclusive-OR Gate Open Collector Product Specification Logic Products TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 18ns 6.1mA 74LS136 ORDERING CODE FUNCTION TABLE OUTPUT INPUTS A B Y L L H H L H L H

74LS09 N

Contextual Info: Signelics | 74LS09 Gates Quad Two-Input AND Gate Open Collector Product Specification Logic Products TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 23ns 4.3 74LS09 ORDERING CODE PACKAGES COMMERCIAL RANGE Vcc = 5V ±5% ; T a = 0°C to +70°C

74LS622

Abstract: 74LS621
Contextual Info: 74LS621, LS622 Signetics Transceivers 'LS621 Non-Inverting Octal Bus Transceiver Open Collector 'LS622 Inverting Octal Bus Transceiver (Open Collector) Product Specification Logic Products FEATURES • Octal bidirectional bus Interface • Open-coliector output

quad exclusive-or/NOR gate

Abstract: 1N3064 1N916 74LS 74S135 N74S135N
Contextual Info: Signetics 74S 135 Gate Quad E xclusive O R/NO R Gate Product Specification L o g ic P rod ucts TYPE T Y P IC A L P R O P A G A T IO N D E LA Y T Y P IC A L S U P P LY C U R R E N T T O T A L 9ns 65m A 74S 135 ORDERING CODE FUNCTION TABLE IN PU TS O U TP U T