0025F Search Results

MIOP42115

Abstract: 5962-XXXXXZZ qml-38535 QML-38534 PA10M
Contextual Info: DESC FORM 193 • U-S GOVfftNMtOT MINTING O fflC I l « 7 - 7 4 t - 1 2 * 4 0 f l 1 SEP 87 D IS TR IB U T IO N ST A T EM E N T A. 5962-E323 Approved lor public release; distribution Is unlimited. •I T004706 0025fl03 ^ E O ■ 1. SCOPE 1.1 Scope. This drawing forme a part of a one part - one part ixnber documentation system see

d 1556 transistor

Contextual Info: • bbS3T31 0025fc.Qfl ISM « A P X N AMER PHILIPS/DISCRETE BSS64 b?E 3> HIGH VOLTAGE N-P-N TRANSISTORS Silicon planar epitaxial transistor in a microminiature plastic envelope intended for application in thick and thin-film circuits. This transistor is intended fo r high-voltage general purpose and switching

Contextual Info: • b L 5 3^31 0025flb3 30"! N AMER PHILIPS/DISCRETE APX L7E D PM B T3904 yv SILICON EPITAXIAL TRANSISTORS N-P-N transistors in a microminiature SMD plastic envelope intended for surface mounted applications. They are primarily intended for use in telephony and professional communication equipment.

MARKING CODE SMD IC

Abstract: BoN SOT-23 smd transistor marking PA DD25 PMBT3904
Contextual Info: • bbSBTBl 0025flb3 N AMER PHILIPS/DISCRETE ■ APX PMBT3904 b7E D SILICO N EPITAXIAL T R A N SISTO R S N-P-N transistors in a m icrom iniature S M D plastic envelope intended fo r surface m ounted applications. T h e y are prim arily intended fo r use in telephony and professional com m unication equipment.

CY7B9910

Abstract: CY7B9920
Contextual Info: fax id: 3516 CY7B9910 CY7B9920 Low Skew Clock Buffer Block Diagram Description Features • • • • • • • • • Phase Frequency Detector and Filter All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation Zero input to output delay

CY7B9910

Abstract: CY7B9920
Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Features • • • • • • • • • Block Diagram Description All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation Zero input to output delay 50% duty-cycle outputs Outputs drive 50Ω terminated lines

Contextual Info: CY7B991 CY7B992 PRELIMINARY CYPRESS SEMICONDUCTOR Programmable Skew Clock Buffer PSCB Features Functional Description • Output pair skew < 100 ps typical (250 max.) • All outputs skew <250 ps typical (500 max.) • 3.75- to 80-MHz output operation • User-selectable output functions

Contextual Info: S i GEC PLESSEY s I M I t O l\ I L C I O u s SP8402 VERY LOW PHASE NOISE DIVIDE BY 2N The SP8402 is a very low phase noise dividerwhich divides by powers of two. The SO, S1, S2 data inputs select the division ratio in the range 2 1 to 28. Special circuits techniques

Contextual Info: Datasheet R8C/38T-A Group RENESAS MCU 1. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Overview 1.1 Features The R8C/38T-A Group of single-chip microcontrollers MCUs incorporates the R8C CPU core, which provides sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, the CPU core is capable of

Contextual Info: HM514405C Series Preliminary 1,048,576-word x 4-bit Dynamic Random Access Memory HITACHI The Hitachi HM 514405C is a CMOS dynamic RAM o rganized 1,048,576 w ords x 4 bits. HM514405C has realized higher density, higher performance and various functions by employing

Contextual Info: Data Sheet February 1994 ; ^ AT&T Microelectronics FE200-Series Power Modules: dc-dc Converters; 38 Vdc to 60 Vdc Input, 200 W Features High efficiency: 82.5% typical FE200A9 High power density. 33 W in3 (FE200A9, B9) Parallel operations with load sharing

Contextual Info: NOTES' 1.0 MATERIALS' ALL PER M IL-PRF-39012 1.1 HDUSING' STAINLESS STEEL PER ASTM-A582, TYPE 303. 1.2 CENTER CONTACT' BERYLLIUM COPPER ROD ALLDY C172, PER ASTM-B194. 1.3 DIELECTRIC! PTFE FLUGRDCARBON PER ASTM-D1457. 2.0 PLATING' ALL PER MIL-PRF-39012 2.1 HDUSING' PASSIVATED PER M IL-F-14072

CY7B9910

Abstract: CY7B9920
Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Features • All outputs skew <100 ps typical 250 max. ■ 15 to 80 MHz output operation ■ Zero input to output delay The completely integrated PLL enables “zero delay” capability. External divide capability, combined with the internal PLL, allows

R5F21368snfp

Abstract: 06B2D 0025DH 00285H
Contextual Info: Datasheet R8C/36T-A Group RENESAS MCU 1. R01DS0055EJ0100 Rev.1.00 Dec 09, 2011 Overview 1.1 Features The R8C/36T-A Group of single-chip microcontrollers MCUs incorporates the R8C CPU core, which provides sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, the CPU core is capable of

06B2D

Abstract: p9530 0023AH 0025DH 00285H
Contextual Info: Datasheet R8C/38T-A Group RENESAS MCU 1. R01DS0081EJ0100 Rev.1.00 Dec 09, 2011 Overview 1.1 Features The R8C/38T-A Group of single-chip microcontrollers MCUs incorporates the R8C CPU core, which provides sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, the CPU core is capable of

R5F21368snfp

Abstract: R5F21368 r5f2136csnfp 0025DH 00285H
Contextual Info: Preliminary Datasheet Specifications in this document are tentative and subject to change. R8C/36T-A Group RENESAS MCU 1. R01DS0055EJ0001 Rev.0.01 Jan 28, 2011 Overview 1.1 Features The R8C/36T-A Group single-chip microcontrollers MCUs incorporate the R8C CPU core, which provides

CY7B991

Contextual Info: CY7B991 CY7B992 Programmable Skew Clock Buffer Programmable Skew Clock Buffer Features Functional Description • All output pair skew <100 ps typical 250 ps maximum ■ 3.75 MHz to 80 MHz output operation ■ User selectable output functions ❐ Selectable skew to 18 ns

Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Features • All outputs skew <100 ps typical 250 max. ■ 15 to 80 MHz output operation ■ Zero input to output delay The completely integrated PLL enables “zero delay” capability. External divide capability, combined with the internal PLL, allows

Contextual Info: CY7B991 CY7B992 Programmable Skew Clock Buffer Features Functional Description • All output pair skew <100 ps typical 250 maximum ■ 3.75 to 80 MHz output operation ■ User selectable output functions ❐ Selectable skew to 18 ns ❐ Inverted and non-inverted

Contextual Info: CY7B991 CY7B992 Programmable Skew Clock Buffer Features Functional Description • All output pair skew <100 ps typical 250 maximum ■ 3.75 to 80 MHz output operation ■ User selectable output functions ❐ Selectable skew to 18 ns ❐ Inverted and non-inverted

Contextual Info: NOTES: 1.0 MATERIALS: 1.1 HOUSING & NUT: STAINLESS STEEL PER ASTM-A582, TYPE 303. 1.2 CENTER CONTACT: BERYLLIUM COPPER ROD ALLOY C172, PER ASTM -B196. 2.0 PLATING: 2.1 HOUSING & NUT: PASSIVATED PER M IL -F -1 4 0 7 2 AND Q Q -P -3 5 . 2.2 CENTER CONTACT: GOLD PER M IL-G -4 5 2 0 4 ,

CY7B9910

Abstract: CY7B9920
Contextual Info: CY7B9910 CY7B9920 W ances as low as 50 while delivering miniĆ mal and specified output skews and fullĆ swing logic levels CY7B9910 TTL or CY7B9920 CMOS . Features D All outputs skew <100 ps typical (250 max.) D D D D D D D 15Ć to 80ĆMHz output operation

Contextual Info: MITSUBISHI LSlS M5M5256CP,FP,KP,VP,RV-85LL,-85XL, -10LL.-10XL 262144-BIT 32768-WORD BY 8-BIT CM0S STATIC RAM DESCRIPTION This M5M5256CP, FP, KP.VP.RV is a 262144-bit CMOS static RAMs organized as 32768-words by 8 - bits which is fabricated using high-performance 3 polysilicon CMOS

Contextual Info: MITSUBISHI LSIs M 5 M 4 V 1 6 1 6 0 B J ,T P ,R T - 6 ,- 7 ,- 8 ,- 6 S ,- 7 S ,- 8 S _ FAST PAGE MODE 16777216-BIT 1048576-WQRP BY 16-BIT DYNAMIC RAM DESCRIPTION This is a family of 1048576-word by 16-bit dynamic RAMS, fabricated with the high performance CMOS process,and is ideal for