128KX Search Results

alarm clock IC

Abstract: bq4842y
Contextual Info: bq4842Y RTC Module with 128Kx8 NVSRAM Features General Description >• I n te g r a t e d SRAM, re a l-tim e clock, CPU supervisor, crystal, pow er-fail control circuit, and battery The bq4842Y RTC Module is a non­ volatile 1,048,576-bit SRAM organ­ ized as 131,072 words by 8 bits with

FM28V100-TG

Abstract: FM28V100-TGTR tca 335 A
Contextual Info: FM28V100 1Mbit Bytewide F-RAM Memory Features 1Mbit Ferroelectric Nonvolatile RAM • Organized as 128Kx8  High Endurance 100 Trillion 1014 Read/Writes  NoDelay Writes  Page Mode Operation to 33MHz  Advanced High-Reliability Ferroelectric Process

IBM0418A41NLAB

Abstract: IBM0418A81NLAB IBM0436A41NLAB IBM0436A81NLAB
Contextual Info: IBM0436A41NLAB IBM0418A41NLAB IBM0418A81NLAB IBM0436A81NLAB 8Mb 256Kx36 & 512Kx18 and 4Mb (128Kx36 & 256Kx18) SRAM . Features • 8Mb: 256K x 36 or 512K x 18 organizations 4Mb: 128K x 36 or 256K x 18 organizations • Registered outputs • 30 Ω drivers

K7A401800B-QC

Abstract: K7A401809B K7A401809B-QC K7A403200B-QC K7A403209B K7A403209B-QC K7A403609B K7B401825B-QC K7B403225B-QC
Contextual Info: K7A403609B K7A403209B K7A401809B 128Kx36/x32 & 256Kx18 Synchronous SRAM Document Title 128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM Revision History History Draft Date Remark 0.0 1. Initial draft May. 15. 2001 Preliminary 0.1 1. Changed DC parameters

K7A401800B

Abstract: K7A401800B-QC K7A401809B-QC K7A403200B K7A403200B-QC K7A403209B-QC K7A403600B K7B401825B-QC K7B403225B-QC
Contextual Info: K7A403600B K7A403200B K7A401800B 128Kx36/x32 & 256Kx18 Synchronous SRAM Document Title 128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM Revision History History Draft Date Remark 0.0 1. Initial draft May. 15. 2001 Preliminary 0.1 1. Changed DC parameters

IBM0418A8ACLAB

Abstract: IBM0436A4ACLAB IBM0436A8ACLAB IBM0418A4ACLAB
Contextual Info: . IBM0418A4ACLAB IBM0436A8ACLAB Preliminary IBM0418A8ACLAB IBM0436A4ACLAB 8Mb 256Kx36 & 512Kx18 and 4Mb (128Kx36 & 256Kx18) SRAM Features • 8Mb: 256K x 36 or 512K x 18 organizations 4Mb: 128K x 36 or 256K x 18 organizations • 0.25 Micron CMOS technology

K7N401801B

Abstract: K7N403601B
Contextual Info: K7N403601B K7N401801B 128Kx36 & 256Kx18 Pipelined NtRAMTM Document Title 128Kx36 & 256Kx18-Bit Pipelined NtRAMTM Revision History History Draft Date Remark 0.0 1. Initial document. May. 15. 2001 Preliminary 0.1 1. Changed DC parameters Icc ; from 350mA to 290mA at -16,

CY7C1350

Abstract: IDT71V546 MCM63Z736
Contextual Info: fax id: 1103 CY7C1350 PRELIMINARY 128Kx36 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT devices IDT71V546, MT55L128L36P and MCM63Z736 • Supports 143-MHz bus operations with zero wait

IBM0418A4ANLAB

Abstract: IBM0418A8ANLAB IBM0436A4ANLAB IBM0436A8ANLAB
Contextual Info: . Preliminary IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb 256Kx36 & 512Kx18 and 4Mb (128Kx36 & 256Kx18) SRAM Features • 8Mb: 256K x 36 or 512K x 18 organizations 4Mb: 128K x 36 or 256K x 18 organizations • 0.25µ CMOS technology • Synchronous Register-Latch Mode of Operation

IBM0418A41XLAB

Abstract: IBM0418A81XLAB IBM0436A41XLAB IBM0436A81XLAB
Contextual Info: . Preliminary IBM0418A81XLAB IBM0436A81XLAB IBM0418A41XLAB IBM0436A41XLAB 8Mb 256Kx36 & 512Kx18 and 4Mb (128Kx36 & 256Kx18) SRAM Features • 8Mb: 256K x 36 or 512K x 18 organizations 4Mb: 128K x 36 or 256K x 18 organizations • 0.25 Micron CMOS technology

7C1351-40

Abstract: 7C1351-50 7C1351-66 CY7C1351 IDT71V547 MCM63Z737
Contextual Info: fax id: 1102 CY7C1351 PRELIMINARY 128Kx36 Flow-Through SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT devices IDT71V547, MT55L128L36F and MCM63Z737 • Supports 66-MHz bus operations with zero wait states

TAA 310A

Abstract: KM681000BLP-7L 128k x8 SRAM TSOP km681000blp-7 KM681000B KM681000BL KM681000BLE KM681000BL-L
Contextual Info: KM681000B Family CMOS SRAM 128Kx8 bit High Speed CMOS Static RAM FEATURE SUMMARY GENERAL DESCRIPTION • Process Technology: 0.6 um CMOS • Organization : 128K x 8 • Power Supply Voltage : Single 5V +/-10% • Low Data Retention Voltage : 2V Min • Three state output and TTL Compatible

KM68U1000B

Abstract: KM68V1000B
Contextual Info: CMOS SRAM KM68V1000B, KM68U1000B Family 128Kx8 bit Low Power & Low Vcc CMOS Static RAM GENERAL DESCRIPTION FEATURE SUMMARY • Process Technology: 0.6 um CMOS • Organization : 128Kx8 • Power Supply Voltage KM68V1000B fa m ily : 3.3V +/- 0.3V KM68U1000B family : 3.0V +/- 0.3V

Contextual Info: CMOS STATIC RAM 1 MEG 128KX 8-BIT ADVANCE INFORMATION IDT71024 Integrated Device Technology, Inc. FEATURES: The IDT71024 uses eight bidirectional input/output lines to provide simultaneous access to all bits in a word and has an output enable (OE) pin which operates as fast as 15ns.

Contextual Info: LOW POWER 2V CMOS SRAM 1 MEG 128KX 8-BIT ADVANCE INFORMATION IDT71T024 I n te g r a te d D e v iz e T e c h n o lo g y , l i e . FEATURES: DESCRIPTION: • 128K x 8 Organization • Wide Operating Voltage Range: 1.8V to 2.7V • Commercial (0° to 70°C) and Industrial (0° to 70°C)

Contextual Info: LOW POWER 3V CMOS SRAM 1 MEG 128Kx 8-BIT ADVANCE INFORMATION IDT71V024L Integrated D e v ic e T e ch n o lo g y, Inc. FEATURES: DESCRIPTION: • • • • • • • The ID T71V024L is a 1,048,576-bit very low-pow er Static RAM organized as 1 2 8 K x 8 . It is fabricated using ID T’s highreliability CMOS technology. This state-of-the-art technology,

Contextual Info: H Y 6 2 8 1 0 0 A -I •HYUNDAI S e r ie s 128KX 8-bit CMOS SRAM PRELIMINARY DESCRIPTION The HY628100A-I is a high-speed, low power and 131,072 x 8-bits CMOS static RAM fabricated using Hyundai’s high performance twin tub CMOS process technology. This high reliability process coupled with innovative circuit

Contextual Info: I = = = = •= Preliminary IBM0418A81QLAA IBM0418A41 QLAA IBM0436A81QLAA IBM0436A41QLAA 8Mb 256Kx36 & 512x18 and 4Mb (128Kx36 & 256Kx18) SRAM Features • 256K x 36 or 512K x 18 organizations • Registered Outputs • 128K x 36 or 256K x 18 organizations

Contextual Info: I = =• = Preliminary IBM0418A80QLAB IBM0418A40QLAB IBM0436A80QLAB IBM0436A40QLAB 8Mb 256Kx36 & 512x18 and 4Mb (128Kx36 & 256Kx18) SRAM Features • 256K x 36 or 512K x 18 Organizations • Registered Addresses, W rite Enables, Synchro­ nous Select, and Data Ins.

AB26S

Abstract: 7C109A CY7C109 CY7C109A
Contextual Info: CY7C109A PRELIMINARY l ^wSSQBBSf S S ySSt Ì p YJe JkP XRI- XjiïJF ^ 128KX 8 Static RAM Features Functional Description • H ighspeed The CY7C109A is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable

68 1103

Abstract: KM681000BL A14F
Contextual Info: CMOS SRAM KM681000BL / L-L 128Kx8 Bit High Speed CMOS Static RAM FEATURES GENERAL DESCRIPTION The KM 681000BUBL-L is a 1,048,576-bit high-speed Static Random Access Memory organized as131,072 words by 8 bits. The device is fabricated using Samsung's advanced

CY7C1009

Abstract: 7C1009 A14C
Contextual Info: PRELIMINARY r y f|pPA RJL- lrP Anni I CY7C1009 128Kx 8 Static RAM Features Functional Description • Highspeed — tAA = 12 ns • CMOS for optimum speed/power • Low active power — 1020 mW • Low standby power — 250 mW The CY7C1009 is a high-performance

bq4013MA-120

Abstract: bq4013Y bq4013YMA-120 bq4013
Contextual Info: bq4013/Y 128Kx8 Nonvolatile SRAM Features General Description ➤ Data retention for at least 10 years without power The CMOS bq4013/Y is a nonvolatile 1,048,576-bit static RAM organized as 131,072 words by 8 bits. The integral control circuitry and lithium energy

FM18L08

Abstract: FM20L08 FM20L08-60-TG
Contextual Info: Preliminary FM20L08 1Mbit Bytewide FRAM Memory – Extended Temp. Features 1Mbit Ferroelectric Nonvolatile RAM • Organized as 128Kx8 • Unlimited Read/Write Cycles • NoDelay Writes • Page Mode Operation to 33MHz • Advanced High-Reliability Ferroelectric Process