25TMB Search Results

CY7C263-35PC

Abstract: 7C261 CY7C263 CY7C26345DMB cerdip z PACKAGE 7C264 C261 CY7C261 CY7C264 f1b0
Contextual Info: CY7C261 CY7C263/CY7C264 CYPRESS Features • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — 20 ns commercial — 25 ns (military) • Low power — 660 mW (commercial) — 770 m\V (military) • Super low standby power (7C261)

L496D

Abstract: 9l reset CY7C331 ST L11922 0423-J
Contextual Info: CY7C331 -W C Y P R E S S Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set,

Contextual Info: Asynchronous Registered EPLD 13 inputs, 12 feedback VO pins, plus 6 shared I/O macrocell feedbacks for a total of 31 true and complementary inpnts High speed: 20 ns maximum tpo Security bit Space-saving 28-pin slim-line DIP package; also available in 28-pin

transistor c331

Abstract: c331 transistor C3318 C3317 C331 C3311 C331 datasheet CY7C331 20HC c331 equivalent
Contextual Info: CY7C331 Asynchronous Registered EPLD Features • Low power — 90 mA typical ICC quiescent • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable — One feedback flip-flop with input coming from the

Contextual Info: CY7C332 ¡W CYPRESS SEMICONDUCTOR 13 in p u t m acrocells, each having: — C om plem entary input — R egister, latch, o r tra n s p a re n t access — Two clock sources Features • • Registered Combinatorial EPLD 12 I/O m acrocells each having: — R egistered, latched, o r tra n s p a re n t

smd code ND

Abstract: 7c263 L43 SMD
Contextual Info: CY7C261 CY7C263/CY7C264 CYPRESS SEMICONDUCTOR • TTL-compatlble I/O • Direct replacement for bipolar PROMs • CMOS for optimum speed/power • Windowed Tor reprogrammability • High speed — 20 ns commercial — 25 ns (military) • Low power — 660 mW (commercial)

C3317

Abstract: L1190 CY7331
Contextual Info: Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coming from the I/O pin — Independent product term set, reset, and clock inputs on all

Contextual Info: CY7C342 CY7C342B CYPRESS SEMICONDUCTOR & 128-Macrocell M A X EPLDs Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • Available in 68-pin HLCC, PLCC, PGA, and Flatpack

C3325

Abstract: l9618 L9680 C3326 L9622 l9742 tunel C3321
Contextual Info: C YP RE SS SEMICONDUCTOR a ML.E D 2S 0^bb2 GQQ7Q33 S Q C Y P "T" ^ ^ CYPRESS SEMICONDUCTOR CY7C332 Registered Combinatorial EPLD 13 input macrocells, each having: — Complementary input — Register, latch, or transparent access — I\vo clock sources 15 ns tpo max.

CERAMIC LEADLESS CHIP CARRIER

Abstract: la crosse technology smd UJ 99 7C245A CY7C245A 0G152
Contextual Info: W CYPRESS Features • • W indowed for reprogram m ability • C M O S for optim um speed/power • • • H igh speed — 15-ns ad dress set-up • — 10-ns clock to output • Low power — 330 m W com m ercial for —25 ns — 660 mW (m ilitary) •

CY7C291A

Abstract: CY7C292A CY7C293A 57C29
Contextual Info: F# CYPRESS Features • Windowed for reprogrammability • CMOS for optimum speed/power • High speed — 20 ns commercial — 25 ns (military) CY7C291A CY7C292A/CY7C293A 2K X 8 Reprogrammable PROM • Direct replacement for bipolar PROMs • Capable o f withstanding >2001V stat­

7C261

Abstract: 7c264
Contextual Info: CY7C261 CY7C263/CY7C264 WÈP CYPRESS 8K x 8 Power-Switched and Reprogrammable PROM floating-gate technology and byte-wide in­ telligent programming algorithms. The CY7C261, CY7C263, and CY7C264 are plug-in replacements for bipolar de­ vices and offer the advantages of lower

CY7C332-25HMB

Abstract: L9646 c3328 L9806 l9634 L9680 L480 L9622 L9626 L9823
Contextual Info: CY7C332 '0 C Y P R E S S F e a tu re s • 12 I/O macrocells each having: — Registered, latched, or transparent array input — A choice of two clock sources — Global or local output enable OE — Up to 19 product terms (PTs) per output — Product terra (PT) output polarity

7C261

Abstract: 7C261-25 C2612 CY7C263-45DC C2613 J-64 CY7C263-35DMB CY7C261 DIODE SMD W12 75 C261
Contextual Info: CYPRESS SEMIC ON DUC TOR MbE D BSfl^bbS □□Qb704 1 n C Y P CY7C261 CY7C263/CY7C264 CYPRESS SEMICONDUCTOR Features 8192 x 8 Power-Switched and Reprogrammable PROM • TTL-compatible I/O • Direct replacement for bipolar PROMs • CMOS for optimum speed/power

transistor c331

Abstract: c331 transistor c331 c331 equivalent C3318 C3319 C3314 c3317 C3311 transistor c331 datasheet
Contextual Info: fax id: 6016 1CY7C331 CY7C331 Asynchronous Registered EPLD Features • Low power — 90 mA typical ICC quiescent • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable

lc 245a

Abstract: DIODE SMD 10 - 25L DIODE SMD 10 25L 7C245A 7c245
Contextual Info: CY7C245A •= CYPRESS • 5V ± 10% V c, commercial and military • I I I.-compatible I/O • Direct replacement for bipolar PROMs • Capable of withstanding greater than 2001V static discharge F e a tu re s • Windowed for reprogrammability • CMOS for optimum speed/power

CY7C263

Abstract: 7C264 7C261 C261 CY7C261 CY7C264 CY7C263-45WC CY7C264-55 cy7c261-45wmb CY7C264-45WMB
Contextual Info: CY7C261 CY7C263/CY7C264 CYPRESS Features • Capable of withstanding greater than 2001V static discharge • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — 20 ns commercial — 25 ns (military) • Low power — 660 mW (commercial)

2SUR

Abstract: CY7C331 L1190 C3317
Contextual Info: CY7C331 ¿F C Y P R E S S Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set, reset, and clock inpnts on all

RQW 130

Abstract: tlOH-tm33X ELLS 110 CY7C331
Contextual Info: i*bE ]> CYPRESS SEMICONDUCTOR B 256*^1.2 DDQ7Q5Q 7 Q C Y P c t 7C33i CYPRESS SEMICONDUCTOR Asynchronous Registered EPLD Features • Tnelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — O ne feedback flip-flop with input

7C293A

Abstract: 7C291A
Contextual Info: CY7C291A CY7C292A/CY7C293A î f CYPRESS Features • Windowed for reprogrammability • CMOS for optimum speed/power • High speed — 20 ns commercial 2K X 8 Reprogrammable PROM The CY7C291A, CY7C292A, and CY7C293A are plug-in replacem ents for bipolar devices and offer the advantages of

Contextual Info: s rs 'w CY7C332 ~ •• = Registered Combinatorial EPLD CYPRESS — SEMICONDUCTOR Features • 12 I/O macrocells each having: — Registered, latched, or transparent array input — A choice of two clock sources — Global or local output enable OE — Up to 19 product terms (PTs) per

c331 equivalent

Abstract: C3317 c331-12 c3311 192x pin diagram c331
Contextual Info: CY7C331 Asynchronous Registered EPLD • Low power — 90 mA typical ICC quiescent Features • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable — One feedback flip-flop with input coming from the I/O