45LMB Search Results

C2665

Abstract: C2668 7c26 C2662 C266 27C64 CY7C266 R1250 C2666
Contextual Info: 1CY 7C26 6 CY7C266 8Kx8 Power-Switched and Reprogrammable PROM Features Functional Description • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — 20 ns commercial — 25 ns (military) • Low power — 660 mW (commercial)

CY7C128A

Abstract: transistor C128 C128A 7C128A-45 7C128A-25
Contextual Info: 1CY 7C12 8A CY7C128A 2K x 8 Static RAM Features Functional Description • Automatic power-down when deselected • CMOS for optimum speed/power • High speed — 15 ns • Low active power — 440 mW commercial — 550 mW (military) • Low standby power

CY7C197

Contextual Info: CY7C197 256Kx1 Static RAM Features vided by an active LOW chip enable CE and three-state drivers. The CY7C197 has an automatic power-down feature, reducing the power consumption by 75% when deselected. • High speed — 12 ns Writing to the device is accomplished when the chip enable

FT6163

Contextual Info: FT6163/FT6163L  Ultra High Speed 8K x 9 Static Cmos Rams FEATURES Data Retention with 2.0V Supply, 10 µA Typical Current 7163L Military) Common I/O Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved)

CY7C263-35PC

Abstract: 7C261 CY7C263 CY7C26345DMB cerdip z PACKAGE 7C264 C261 CY7C261 CY7C264 f1b0
Contextual Info: CY7C261 CY7C263/CY7C264 CYPRESS Features • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — 20 ns commercial — 25 ns (military) • Low power — 660 mW (commercial) — 770 m\V (military) • Super low standby power (7C261)

0148-t

Abstract: CY7C148 CY7C149 CY7C148-25DC up c1482 0148t L5045 CY7C148-35PC CY7C148-35DC MU 350
Contextual Info: CYPRESS SEMICONDUCTOR MbE D B DODbMll 2 5 0 ^ 2 b EÏCYP CY7C148 CY7C149 CYPRESS SEMICONDUCTOR Automatic power-down when dese­ lected 7C148 CMOS for optimum speed/power 25-ns access time Low active power — 440 mW (commercial) — 60S m\V (military) Low standby power (7C148)

K73 Package

Abstract: 3 phase inverter schematic diagram 7C166 CY7C164A CY7C166A CI64A CY7C164A-45DMB
Contextual Info: 4bE D CYPRESS SEM IC ON DU CT OR □ - p q & eSÛ'IbbE OQObMfiS 2 R3CYP .r S - l O C Y 7 C I6 4 A C Y 7 C 1 6 6 A ";ui'./^CTPRESS , _ SEMICONDUCTOR 16,384 x 4 Static R/W RAM Features Functional Description • Automatic power-down when

7C192-12

Abstract: 7C192-15 7C192-20 A10C CY7C191 CY7C192 CY7C192-25PC
Contextual Info: MbE D CYPRESS SEMICON DUC TOR B 250^fc,b2 OOQfc.1,42 3 E 3 C Y P CY7C191 CY7C192 CYPRESS SEMICONDUCTOR Features • Automatic power-down when deselected • Transparent write 7C19X • CMOS for optimum speed/power • H ighspeed — tM = 25 ns • Low active power

7C192-12

Abstract: 7C192-15 A10C CY7C191 CY7C192 CY7C192-25PC
Contextual Info: CY7C191 CY7C192 ir CYPRESS 64K x 4 Static RAM with Separate I/O Features Functional Description • High speed T he CY7C191 and CY7C192 are high­ perform ance CM OS static RAM s orga­ nized as 65,536 x 4 bits with separate I/O. Easy m em ory expansion isprovided by ac­

7C168A

Abstract: CY7C168A CY7C169A 7C168 CY7C168A-25LMB
Contextual Info: CYPRESS SEM ICOND UC TO R MhE D ^ B 250^2 GODbSlM 5 O C V P ,7 ^ CY7C168A CY7C169A <VH 'V? -O 2> CYPRESS SEMICONDUCTOR Features Automatic pow er-dow n when dese­ lected 7C168A CMOS for optimum speed/power High speed — U a = 15 n s — tACE = 10ns(7C169A)

cy7c131-55nc

Abstract: ZT12 CY7C130 CY7C131 CY7C140 CY7C141 IDT7130 IDT7140
Contextual Info: CY7C130/CY7C131 CY7C140/CY7C141 W CYPRESS Features • 0.8-micron CMOS for optimum speed/power • Automatic power-down • TTL compatible • Capable o f withstanding greater than 2001V electrostatic discharge • Fully asynchronous operation • Master CY7C130/CY7C131 easily ex­

automaticpower change over switch circuit diagram

Abstract: CY7C185 CY7C185A
Contextual Info: CY7C185A '* C YPRESS 8K x 8 Static RAM Features Functional D escription • High speed — 20 ns • CMOS for optimum speed/power T he CY7C185A is a high-perform ance CMOS static RA M organized as 8192 words by 8 bits. Easy mem ory expansion is provided by an active LO W chip enable

P4C148

Abstract: P4C149
Contextual Info: P4C148, P4C149 ULTRA HIGH SPEED 1K x 4 STATIC CMOS RAMS FEATURES Full CMOS, 6T Cell Two Options – P4C148 Low Power Standby Mode – P4C149 Fast Chip Select Control High Speed Equal Access and Cycle Times – 10/12/15/20/25/35/45/55 ns (Commercial) – 15/20/25/35/45/55 ns (P4C148 Military)

Contextual Info: CY7C148 CY7C149 CYPRESS IK x 4 Static RAM Features • TTL-compatible inputs and outputs • Automatic power-down when dese­ lected 7C148 • CMOS for optimum speed/power • 25-ns access time • Low active power — 440 mW (commercial) — 605 mW (military)

CY7C185A-20LMB

Abstract: C185A CY7C185 CY7C185A 624a2
Contextual Info: 1CY 7C18 5A CY7C185A 8K x 8 Static RAM Features • High speed — 20 ns • CMOS for optimum speed/power • Low active power — 743 mW • Low standby Power — 220 mW • TTL-compatible inputs and outputs • Easy memory expansion with CE1, CE2 and OE features

24-Pin Plastic DIP

Abstract: 64 CERAMIC LEADLESS CHIP CARRIER LCC diode Lz 66 transistor smd code wz P4C188 P4C188L
Contextual Info: P4C188/188L P4C188/P4C188L ULTRA HIGH SPEED 16K x 4 STATIC CMOS RAMS FEATURES Single 5V±10% Power Supply Data Retention with 2.0V Supply P4C188L Military Three-State Outputs TTL/CMOS Compatible Outputs Fully TTL Compatible Inputs Standard Pinout (JEDEC Approved)

Contextual Info: P4C188/P4C188L ULTRA HIGH SPEED 16K x 4 STATIC CMOS RAMS FEATURES Single 5V±10% Power Supply Data Retention with 2.0V Supply P4C188L Military Three-State Outputs TTL/CMOS Compatible Outputs Fully TTL Compatible Inputs Standard Pinout (JEDEC Approved) – 22-Pin 300 mil DIP

Contextual Info: P4C163/P4C163L ULTRA HIGH SPEED 8K x 9 STATIC CMOS RAMS FEATURES Data Retention with 2.0V Supply, 10 µA Typical Current P4C163L Military Common I/O Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved) – 28-Pin 300 mil DIP, SOJ – 28-Pin 350 x 550 mil LCC

Contextual Info: P4C168, P4C169, P4C170 ULTRA HIGH SPEED 4K x 4 STATIC CMOS RAMS FEATURES Full CMOS, 6T Cell Fully TTL Compatible, Common I/O Ports High Speed Equal Access and Cycle Times – 12/15/20/25/35ns (Commercial) – 20/25/35/45/55/70ns (P4C168 Military) Three Options

Contextual Info: P4C187/P4C187L ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS FEATURES Full CMOS, 6T Cell Data Retention with 2.0V Supply P4C187L Military High Speed (Equal Access and Cycle Times) – 10/12/15/20/25 ns (Commercial) – 12/15/20/25/35 ns (Industrial) – 15/20/25/35/45 ns (Military)

Contextual Info: P4C164 ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAMS FEATURES Data Retention with 2.0V Supply, 10 A Typical Current P4C164L Military Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 8/10/12/15/20/25/35/70/100 ns (Commercial) – 10/12/15/20/25/35/70/100 ns(Industrial)

Contextual Info: P4C164 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: SRAM115 P4C164 ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAMS REV. ISSUE DATE ORIG. OF CHANGE OR 1997 DAB New Data Sheet A Oct-05 JDB Change logo to Pyramid B Jun-06 JDB Added 28-pin ceramic DIP C Aug-06 JDB Added Lead Free Designation

LC 7258

Abstract: 7C266 203CE
Contextual Info: CY7C266 / CYPRESS 8K x 8 Power-Switched and Reprogrammable PROM Features • TTL-compatible I/O • CMOS for optimum speed/power • Direct replacement for 27C64 EPROMs • Windowed for reprogrammability • High speed — 20 ns commercial — 25 ns (military)

6198A

Contextual Info: FT6198 L FT6198A(L) Ultra High Speed 16K x 4 Static CMOS Ram FEATURES Output Enable & Chip Enable Control Functions – Single Chip Enable FT6198 – Dual Chip Enable FT6198A Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 10/12/15/20/25 ns (Commercial)