25LMB Search Results

CY7C187

Abstract: CY7C187A
Contextual Info: CY7C187A 64K x 1 Static RAM Features provided by an active LOW chip enable CE and three-state drivers. The CY7C187A has an automatic power-down feature, reducing the power consumption by 55% when deselected. • High speed — 20 ns • CMOS for optimum speed/power

C2665

Abstract: C2668 7c26 C2662 C266 27C64 CY7C266 R1250 C2666
Contextual Info: 1CY 7C26 6 CY7C266 8Kx8 Power-Switched and Reprogrammable PROM Features Functional Description • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — 20 ns commercial — 25 ns (military) • Low power — 660 mW (commercial)

C401 diode

Abstract: 10DC IR transistor 10dc ir C4016 C4019 C401 CY7C401 CY7C402 CY7C403 C4013
Contextual Info: CY7C401/CY7C403 CY7C402/CY7C404 64 x 4 Cascadable FIFO 64 x 5 Cascadable FIFO Features words. Both the CY7C403 and CY7C404 have an output enable OE function. • 64 x 4 (CY7C401 and CY7C403) 64 x 5 (CY7C402 and CY7C404) High-speed first-in first-out memory (FIFO)

CY7C128A

Abstract: transistor C128 C128A 7C128A-45 7C128A-25
Contextual Info: 1CY 7C12 8A CY7C128A 2K x 8 Static RAM Features Functional Description • Automatic power-down when deselected • CMOS for optimum speed/power • High speed — 15 ns • Low active power — 440 mW commercial — 550 mW (military) • Low standby power

CY7C197

Contextual Info: CY7C197 256Kx1 Static RAM Features vided by an active LOW chip enable CE and three-state drivers. The CY7C197 has an automatic power-down feature, reducing the power consumption by 75% when deselected. • High speed — 12 ns Writing to the device is accomplished when the chip enable

FT6163

Contextual Info: FT6163/FT6163L  Ultra High Speed 8K x 9 Static Cmos Rams FEATURES Data Retention with 2.0V Supply, 10 µA Typical Current 7163L Military) Common I/O Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved)

7cl6

Abstract: D-2501 CY7C161A CY7C162 CY7C162A
Contextual Info: CYPRESS SEMICONDUCTOR 4bE » B SSfl'lbfe.S □ QQbMSb b q c y p CY7C161A CY7C162A • - j/ "— = 16,384 x 4 Static RAV RAM Separate I/O SEMICONDUCTOR Features • Automatic power-down when dese­ lected • Transparent write 7C161A • CMOS for optimum speed/power

CY7C263-35PC

Abstract: 7C261 CY7C263 CY7C26345DMB cerdip z PACKAGE 7C264 C261 CY7C261 CY7C264 f1b0
Contextual Info: CY7C261 CY7C263/CY7C264 CYPRESS Features • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — 20 ns commercial — 25 ns (military) • Low power — 660 mW (commercial) — 770 m\V (military) • Super low standby power (7C261)

tle 6261 g

Abstract: AoL-12L S-108 SEM 238 TLE TSOP CY7B144 CY7B145 B08L
Contextual Info: 4bE D CYPRESS SEMICONDUCTOR • ESfi^bbS 00ab3SG 2 E3CYP 'T-% -Zl> -\ Z_ PRELIMINARY & CYPRESS ill — ^ s ? SEMICONDUCTOR 8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Features Functional Description • 0.8-mlcron BiCMOS for high per­ formance • High-speed access

7C192-12

Abstract: 7C192-15 7C192-20 A10C CY7C191 CY7C192 CY7C192-25PC
Contextual Info: MbE D CYPRESS SEMICON DUC TOR B 250^fc,b2 OOQfc.1,42 3 E 3 C Y P CY7C191 CY7C192 CYPRESS SEMICONDUCTOR Features • Automatic power-down when deselected • Transparent write 7C19X • CMOS for optimum speed/power • H ighspeed — tM = 25 ns • Low active power

c46cm

Abstract: CY7C460 CY7C462 CY7C464 IDT7205 IDT7206
Contextual Info: CY7C460 CY7C462 CY7C464 m .W C Y P R E S S C ascadable 8 K x 9 F I F O C ascadable 16K x 9 FIFO C ascadable 3 2 K x 9 FIFO Features • • • • • • • • • • • • • • • data outputs go to the high-impedance Functional Description state when R is H IG H .

CY7C225A

Contextual Info: CY7C225A '= C Y P R E S S Features • CMOS for optimum speed/power • High speed — 18 ns address set-up — 12 ns clock to output • Low power — 495 mW commercial — 660 mW (military) • Synchronous and asynchronous out­ put enables • On-chip edge-triggered registers

7C192-12

Abstract: 7C192-15 A10C CY7C191 CY7C192 CY7C192-25PC
Contextual Info: CY7C191 CY7C192 ir CYPRESS 64K x 4 Static RAM with Separate I/O Features Functional Description • High speed T he CY7C191 and CY7C192 are high­ perform ance CM OS static RAM s orga­ nized as 65,536 x 4 bits with separate I/O. Easy m em ory expansion isprovided by ac­

7C168A

Abstract: CY7C168A CY7C169A 7C168 CY7C168A-25LMB
Contextual Info: CYPRESS SEM ICOND UC TO R MhE D ^ B 250^2 GODbSlM 5 O C V P ,7 ^ CY7C168A CY7C169A <VH 'V? -O 2> CYPRESS SEMICONDUCTOR Features Automatic pow er-dow n when dese­ lected 7C168A CMOS for optimum speed/power High speed — U a = 15 n s — tACE = 10ns(7C169A)

AB26S

Abstract: 7C109A CY7C109 CY7C109A
Contextual Info: CY7C109A PRELIMINARY l ^wSSQBBSf S S ySSt Ì p YJe JkP XRI- XjiïJF ^ 128KX 8 Static RAM Features Functional Description • H ighspeed The CY7C109A is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable

CY7C197

Abstract: CV7C197
Contextual Info: MbE D n " T CYPRESS SEMICONDUCTOR Features Automatic power-down when deselected CMOS for optimum speed/power Highspeed — 20ns Low active power — 880 mW Low standlgr power — 220 mW TlX-compatible imputs and outputs Capable ofwithstanding greater than

CY7C1009

Abstract: 7C1009 A14C
Contextual Info: PRELIMINARY r y f|pPA RJL- lrP Anni I CY7C1009 128Kx 8 Static RAM Features Functional Description • Highspeed — tAA = 12 ns • CMOS for optimum speed/power • Low active power — 1020 mW • Low standby power — 250 mW The CY7C1009 is a high-performance

automaticpower change over switch circuit diagram

Abstract: CY7C185 CY7C185A
Contextual Info: CY7C185A '* C YPRESS 8K x 8 Static RAM Features Functional D escription • High speed — 20 ns • CMOS for optimum speed/power T he CY7C185A is a high-perform ance CMOS static RA M organized as 8192 words by 8 bits. Easy mem ory expansion is provided by an active LO W chip enable

P4C148

Abstract: P4C149
Contextual Info: P4C148, P4C149 ULTRA HIGH SPEED 1K x 4 STATIC CMOS RAMS FEATURES Full CMOS, 6T Cell Two Options – P4C148 Low Power Standby Mode – P4C149 Fast Chip Select Control High Speed Equal Access and Cycle Times – 10/12/15/20/25/35/45/55 ns (Commercial) – 15/20/25/35/45/55 ns (P4C148 Military)

P4C150

Contextual Info: P4C150 ULTRA HIGH SPEED 1K X 4 RESETTABLE STATIC CMOS RAM FEATURES Separate Input and Output Ports Full CMOS, 6T Cell Three-State Outputs High Speed Equal Access and Cycle Times – 10/12/15/20/25 ns (Commercial) – 15/20/25/35 ns (Military) Fully TTL Compatible Inputs and Outputs

P4C147

Contextual Info: P4C147 ULTRA HIGH SPEED 4K x 1 STATIC CMOS RAM FEATURES Full CMOS, 6T Cell Single 5V ± 10% Power Supply High Speed Equal Access and Cycle Times – 10/12/15/20/25 ns (Commercial) – 15/20/25/35 ns (Military) Separate Input and Output Ports Three-State Outputs

Contextual Info: CY7C171A CY7C172A r^ y p p p cc Features F unctional D escription • Automatic power-down when deselected • CMOS for optimum speed/power • High speed — tAA = 15 ns • Transparent write 7C171A • Low active power — 375 mW • Low standby power

Contextual Info: PRELIMINARY SEMCONDUCTOR CY7B138 CY7B139 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Features Functional Description • 0.8-micron BiCMOS for high per­ formance • High-speed access — 15 ns com’l — 25 ns (mil) • Automatic power-down • Fully asynchronous operation

Contextual Info: Asynchronous Registered EPLD 13 inputs, 12 feedback VO pins, plus 6 shared I/O macrocell feedbacks for a total of 31 true and complementary inpnts High speed: 20 ns maximum tpo Security bit Space-saving 28-pin slim-line DIP package; also available in 28-pin