7777Z Search Results

4N500

Abstract: IC 741 cn
Contextual Info: b427555 GG42530 Tfc.7 « N E C E / / MOS INTEGRATED CIR CU IT ju P D 4 2 S 1 6 1 9 0 , 4 2 S 1 7 1 9 0 , 4 2 S 1 8 1 9 0 16 M B IT D Y N A M IC RAM FA S T PA G E M O D E & B Y T E W R IT E M O DE - P R E LIM IN A R Y -D E S C R IP T IO N

SRM-2016

Abstract: SRM2016C SRM2016
Contextual Info: SRM2016 CMOS 16K-BIT STATIC RAM • DESCRIPTION The SRM201612 is a 2,048 words x 8 bits asynchronous, static, random access memory on a monolithic CMOS chip. Its very low standby power requirement makes it ideal for applications requiring non-volatile storage with

ctrdiv16

Abstract: t163
Contextual Info: TOSHIBA TC74ACT161/163 Synchronous Presettable 4-bit Counter 161: Binary, Asynchronous Clear 163: Binary, Synchronous Clear Features: • The TC74AC161 and T163 are advanced high speed CMOS SYNCHRONOUS PRESETTABLE 4-BIT BINARY COUNTERS fabricated w ith silicon gate and double-layer

Contextual Info: Integrated Device TechnoJogy, lie. PRELIMINARY IDT723624 IDT723634 IDT723644 CMOS Sync BiFlFO With Bus-Matching 256 x 36 x 2, 512 x 36 x 2, 1024x36x2 NOTE: There is an errata notice on the last page and the corrections have not been incorporated into this document.

Contextual Info: 3.3 VOLT CMOS SyncBiFlFO WITH BUS-MATCHING 2 5 6 x 3 6 x 2, 512 x 3 6 x 2, 1,024 x 36 x 2_ FEATURES: • Memory storage capacity: IDT72V3624-256 x 36 x 2 IDT72V3634-512 x 36 x 2 IDT72V3644-1,024x36x2 • Clock frequencies up to 83 MHz 8ns access time

BV 3145

Contextual Info: CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36 FE ATURES: • Free-running CLKA and CLKB may be asynchronous or coincident perm its sim ultaneous reading and w riting ot data on a single clock edge • 64 x 36 storage capacity FIFO buttering data trom Port A

Contextual Info: QS7025A PRELIMINARY High-Speed CMOS 8K X 16 QS7025A Asynchronous Dual-Port RAM FEATURES/BENEFITS • • • • • • • • H igh-speed asynchronous dual-port architecture Independent port access and control Access tim es from either port, 25/35/45/55 ns

MN7130

Abstract: MN520 MN5240
Contextual Info: MN5240 /K fJ ? M ic r o 10 and 12-Bit H IG H-SPEED A/D CONVERTERS N e tw o r k s A D IVISION O F U N I T M M CO R PO R ATIO N FEATURES • Fast Conversion Times: 5psec Max for 12 Bits 4.2psec Max for 10 Bits • Complete A/D Function: internal Clock Internal Reference

j477

Abstract: V54C365164VC
Contextual Info: M O S E L V IT E L IC V54C365164VC HIGH PERFORMANCE 143/133/125 MHz 3.3 V 0 L T 4 M X 16 SYNCHRONOUS DRAM 4 BANKS X 1Mbit X 16 PRELIMINARY 7 75 8PC 8 System Frequency fCK 143 MHz 133 MHz 125 MHz 125 MHz Clock Cycle Tim e (tcK 3) 7 ns 7.5 ns 8 ns 8 ns Clock Access Tim e (tAC3) CAS Latency = 3

ST5410

Abstract: pin diagrom of 4 bit up down counters stt4 st5410c cl-gd STS410 1554k
Contextual Info: /TT SGS-THOMSON ST5410 6 * [ S Î It iC T M 0 g S 2B1Q U INTERFACE DEVICE A D V A N C E DATA G EN E R AL FEATURES • SINGLE CHIP 2B1Q LINE CODE TR AN S­ CEIVER ■ SUITABLE FOR BOTH ISDN AND PAIR GAIN APPLICATIO NS ■ MEETS OR EXCEEDS ANSI T 1 .601 -1988

Contextual Info: mDi EDI8465C/P35/45/55 High Speed 256K Monolithic SRAM 64Kx4 Static RAM CMOS, High Speed Monolithic The EDI8465C/P is a high performance CMOS Static RAM organized as 64Kx4 and available in both standard power C and low power (P) versions. Inputs and outputs are TTL compatible and allow for direct

NCC 5551

Abstract: CI 555 data X20C04 X20C05 X20C16 IS555
Contextual Info: Advance Information X20C05 4K 512x8 High Speed AUTOSTORE NOVRAM_ FEATURES DESCRIPTION • Fast Access Time: 35ns, 45ns, 55ns • High Reliability — Endurance: 1,000,000 Store Operations — Retention: 100 Years Minimum • Power-on Recall

R7F7

Contextual Info: Preliminary H M 5216165 S e r ie s 524,2SS-word x 16-blt x 2-bank Syn ch ro n o u s D ynam ic R A M HITACHI All inpuls and outputs are referred to the rising e d g e o f th e c lo c k in p u t. T h e H M 5 2 1 6 1 6 5 is offered in 2 banks for improved performance.

62c3232

Contextual Info: ADE-203-494A Z HM62C3232FP-7 32,768-word x 32-bit Synchronous Fast Static RAM with Burst Counter and Pipelined Data Output HITACHI Features Ordering Information Type No. Access CPU Clock tim e Rate Package HM62C3232FP-7 7 ns • S in g le 3.3 V p o w e r su p p ly (L V T T L )

intel i486

Abstract: IDT7MP6105 7MP6104
Contextual Info: bfiE D I S^N. • • Haas77i a n m s 3 i ?is ■ idt IDT7MP6104 128KB/256KB SECONDARY CACHE MODULE IDT7MP6105 FOR THE INTEL i486 INTEGRATED DEVICE Integrated Device Technology, Inc* FEATURES DESCRIPTION • 128 K B /2 5 6 K B d ire c t m a pped , w rite -th ro u g h , no n-sectored ,

R40 AH

Contextual Info: HM5283206 Series 131,072-word x 32-bit x 2-bank Synchronous Graphic RAM HITACHI ADE-203-223A Z Rev. 1.0 May. 30, 1996 Description All inputs and outputs signals refers to the rising edge of the clock input. The HM5283206 provides 2 banks to realize better performance. 8 column block write function and write per bit function are

42S421

Abstract: I2758 uPD424210-60-G eZ 752 SCZ7 NEC Japan 424210-60 7PP4
Contextual Info: PRELIMINARY DATA SH EET_ / M O S IN T E G R A T E D CIRCUIT ¿/PD42S4210-60-G,424210-60-G 4 M-BIT DYNAMIC RAM 256 K-WORD BY 16-BIT, HYPER PAGE MODE, BYTE READ/WRITE MODE Description The ¿/PD42S4210-60-G,424210-60-G is 262 144 words by 16 bits dynamic CM OS RAMs with optional

ic 7485

Abstract: pin diagram for IC 7485 pin diagram for IC 7485 input id pin diagram ic 7485 7485 aa ci 7485
Contextual Info: PRELIMINARY CYPRESS SEMICONDUCTOR CYM7485 128K Write-Through Secondary Cache Module Features Functional Description • 128-Kbyte direct-mapped, writethrough, zero-wait-state secondary cache module • Operates with 33-MHz Intel 486 pro­ cessors • Uses low-cost CMOS asynchronous

KJh transistor

Abstract: WPD431
Contextual Info: NEC OCT 2 « 1992 ELECTRON DEVICE PRELIMINARY DAT* SHEET MOS INTEGRATED C IR C U IT /¿PD43 1 0 0 2 128K X 9 BIT CMOS STATIC RAM DESCRIPTION The ¿¡PD431002 is a high speed, low power, 128K words by 9 bits CMOS static RAM fabricated with advanced silicon-gate CMOS technology. The «PD431002 is a low standby power device using

multiturn preset potentiometer

Contextual Info: MN5240 10 an d 12-Bit H IG H -S P E E D A /D C O N V E R T E R S MICRO NETWORKS DESCRIPTION • Fast Conversion Times: 5/iSec Max for 12 Bits 4.2/^sec Max for 10 Bits • Complete A/D Function: Internal Clock Internal Reference Input Buffer Short-Cycle Pin

HM5241

Abstract: HM5241605CTT15
Contextual Info: HM5241605C Series Preliminary 131,072-w ord x 16-bit x 2-bank Synchronous Dynam ic RAM H IT A C A ll inputs and outputs are referred to the rising edge of the clock input. The HM5241605C is offered in 2 banks for improved performance. Features • 3.3 V Power supply

rft electronica

Contextual Info: HM52161 65 Series Preliminary 524,288-word x 16-bit x 2-bank Synchronous Dynamic RAM HITACHI A ll inputs and outputs arc referred to the rising edge of the clock input. The H M 5 2 16165 is offered in 2 banks for improved performance. Features Rev. 0.0 Jul. 2 9 ,1 9 9 4

Contextual Info: CY7B134 CY7B135 CY7B1342 CYPRESS 4K x 8 Dual-Port Static RAMs and 4K x 8 Dual-Port Static RAM with Semaphores Features Functional Description • 0.8-micron BiCMOS for high performance • High-speed access — 15 ns commercial — 25 ns (military) • Automatic power-down

77777AV

Abstract: R7F7
Contextual Info: H M 5 2 4 1 6 5 - 1 Preliminary 2 131,072-word x 16-bit x 2-bank Synchronous Dynamic RAM HITACHI A ll inputs and outputs are referred to the rising edge of the clock input. The HM5241605 is offered in 2 banks for improved performance. Features m Rev. 0.0 Jan. 27,1995