EPLD Search Results

7C344-25

Abstract: C344 74HC CY7C344 Signal Path Designer C3445
Contextual Info: CY7C344 32-Macrocell MAX EPLD Features tional I/O pins communicate to one logic array block. In the CY7C344 LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an input, two expanders are used to create an input path. Even if all of the

74151

Abstract: 74151 pin connection C3406 74151 PIN DIAGRAM 74151 waveform counter schematic diagram 74161 programmer EPLD 22v10 5192JM 74151 multiplexer
Contextual Info: 1CY 7C34 0 fax id: 6100 EPL D Family CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDS Features tion of innovative architecture and state-of-the-art process, the MAX EPLDs offer LSI density without sacrificing speed. • Erasable, user-configurable CMOS EPLDs capable of

31-oq

Abstract: 7C342-25 CY7C342-35HMB 7C342-35 CY7C342 CY7C342B OQ11
Contextual Info: CY7C342 CY7C342B rif CYPRESS 128-Macrocell M AX EPLD Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C342

EPLD 5128

Abstract: EPM5128-1 K942
Contextual Info: EPM5128 EPLD Features □ □ □ □ □ H igh-density, 128-macrocell, general-purpose MAX 5000 EPLD High-speed multi-LAB architecture t PD as fast as 25 ns Counter frequencies up to 50 MHz Pipelined data rates up to 62.5 MHz 256 shareable expander product terms "expanders" allowing over

7400series

Abstract: cmos logic 7400 series 7400 family TTL 7400-series EPM5016
Contextual Info: The Complete Industry-Standard Programm able Logic Family MAX 5000 EPLDs 384 EPM5192 tpp = 25 ns - C/> 0> .c o 3 08 EPM5128 tpp —25 ns 256 CO Q. A EPM5130 tpp —25 ns O / ca> D EPM5064, tPD = 25 ns 128 ▲ EPM5032, tPD = 15 ns 64 ▲ EPM5016, tPD = 15 ns

Contextual Info: AN Ù 1=! n ^ !S \ Contents September 1991 Section 5 STG & SAM EPLDs STG & SAM EPLDs: Synchronous State M achine & W aveform G eneration D evices. 189 EPS464 STG EPLD: Synchronous Tim ing G e n e ra to r.191

Contextual Info: /A^b Contents September 1991 Section 4 MAX 7000 EPLDs MAX 7000 EPLD Overview: H igh-Perform ance, High-Pin-Count D e v ice s. 179 A lte ra C o rp o ra tio n

EPM5130

Abstract: 100-Pin Package Pin-Out Diagram D2-3401 EPM 5130
Contextual Info: EPM5130 EPLD □ □ Features □ □ □ □ □ □ □ High-density, 128-macrocell, general-purpose MAX 5000 EPLD 128 m acrocells optim ized for pin-intensive applications, easily integrating over 60 TTL MSI and SSI components High-speed multi-LAB architecture

EP910T

Abstract: altera EP910 EP910-T
Contextual Info: EP910T EPLD Features □ □ a □ □ High-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD = 30 ns Counter frequencies up to 33 MHz Pipelined data rates up to 41 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs Pin-, function-, and programming file-compatible with Altera's EP910

EPLD 5128

Abstract: EPM5120-2
Contextual Info: EPM5128 EPLD Features □ □ H ig h -d en sity 128-m acrocell g en era l-p u rp o se M A X 5000 EPLD 256 sh areab le ex p a n d e r p ro d u ct term s th at allow ov er 32 p ro d u ct term s in a sin gle m acro cell H ig h -sp eed m u lti-L A B a rch itectu re

EP1810-35T

Abstract: ALTERA EP altera EP1810
Contextual Info: Features □ □ □ □ □ □ High-performance, 48-macrocell Classic EPLD Combinatorial speeds with tPD = 20 ns, 25 ns, and 35 ns - Counter frequencies up to 50 MHz Pipelined data rates up to 62.5 MHz Programmable I/O architecture with up to 64 inputs or 48 outputs

J-Lead, QFP ceramic

Abstract: PQFP 176 J-Lead
Contextual Info: EPM5192A EPLD □ Features □ □ Preliminary Information □ □ □ High-performance, second-generation MAX 5000 EPLD developed on an advanced 0.65-m icron CM OS EPROM process High-speed upgrade for existing EPM 5192 designs High-speed multi-LAB architecture

EP610-30

Abstract: EP610-35 EP610-25 EP610 EP610-15 EP610-20 EP6101-10 EP610I
Contextual Info: EP610 EPLD Features * • ■ ■ ■ ■ High-performance, 16-macrocell Classic EPLD Combinatorial speeds with tP D as fast as 10 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs

ep610

Abstract: EP610-30 EP610-35 EP610-25 EP610-15 EP610-20 EP610I P6101
Contextual Info: EPLD Features H igh -perform an ce, 16-m acrocell Classic EPLD C om binatorial speeds w ith as low as 10 ns C oun ter frequencies of up to 100 M H z Pipelined d ata rates of up to 125 M H z Program m able I / O arch itectu re w ith up to 20 inputs o r 16 ou tp uts

Contextual Info: EPM5064 EPLD Features • ■ ■ ■ ■ ■ ■ High-density, 64-macrocell, general-purpose MAX 5000 EPLD High-speed multi-LAB architecture tpu as fast as 15 ns Counter frequencies up to 83.3 MHz Pipelined data rates up to 100 MHz 128 shareable expander product terms "expanders" allowing over

L496D

Abstract: 9l reset CY7C331 ST L11922 0423-J
Contextual Info: CY7C331 -W C Y P R E S S Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set,

K12J

Abstract: 100-PIN CY7C346 CY7C346B f 7400
Contextual Info: CY7C346 CY7C346B 5T CYPRESS 128-Macrocell MAX EPLDs Features Functional Description • 128 macrocells in 8 LABs • 20 dedicated inputs, up to 64 bidirec­ tional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C346

C3402

Abstract: 74151 5128LC-1 74151 PIN DIAGRAM 5128LC-2 74151 8 to 1 74151 pin connection function of 74151 22V10-10C CY7C340
Contextual Info: EPLD CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDs Features • Erasable, user-configurable CMOS EPLDs capable of implementing high-density custom logic functions • 0.8-micron double-metal CMOS EPROM technology CY7C34X • Advanced 0.65-micron CMOS technology to increase

c3431

Abstract: C3438 c3432 CY7C343 c3435 C343-8
Contextual Info: CY7C343 64-Macrocell MAX EPLD Features • • • • • • The CY7C343 contains 64 highly flexible macrocells and 128 expander product terms. These resources are divided into four Logic Array Blocks LABs connected through the Programmable Inter-connect Array (PIA). There are 8 input pins, one that

EDIF200

Abstract: XC4013E-3PQ208C industrial pulse generators schematic Lattice PLSI Temic ulc
Contextual Info: IC DIVISION TEMIC Semiconductors ULC Design Checklist To perform the ULC to FPGA or EPLD feasibility study and conversion rapidly and accurately, please fill out the form below and supply the requested material. All questions must be answered. 1. Customer

Contextual Info: XC7236A 36-Macrocell CMOS EPLD HXILINX Preliminary Product Specifications Features The functional versatility of the traditional programmable logic array architecture is enhanced through additional gating and control functions available in an Arithmetic Logic Unit ALU in each Macrocell. Dedicated fast arith­

Contextual Info: flX IU N XC7336 36-Macrocell CMOS EPLD X Preliminary Product Specifications Features General Description • The XC7336 is a member of the Xilinx Dual-Block EPLD family. It consists of four Fast Function Blocks intercon­ nected by a central Universal Interconnect Matrix UIM .

Contextual Info: XC7354 54-Macrocell CMOS EPLD Product Specifications Features The Universal Interconnect Matrix connects the Function Blocks to each other and to all input pins, providing 100% connectivity between the Function Blocks. This allows logic functions to be mapped into the Function Blocks and

Contextual Info: AT18V8Z Features • 20-pin Universal EPLD • Virtually Zero Standby Power • Functional Replacement for Common 20-Pin Programmable Devices Io l = 24 mA • High Performance CMOS EPROM Cell Technology Erasable Reconfigurable 100% Testable • 25 ns and 35 ns Max Propagation Delay Commercial