OQ11 Search Results

cq837

Contextual Info: 4J« *- »t TOSHIBA HYBRID D IG ITA L INTcGRATED CIRCUIT INTEGRATED CIRCUIT TO SHIBA THM 364080AS THM 364080ASG TECHNICAL DATA - 60. 70. 80, 10 - 60, 70, 80. 10 TENTATIVE DATA 4*194,304 W O R D S X 36 BIT D YN AM IC RA M MODULE DESCRIPTION The THM364080AS/ASG is a 4,194,304 words by 36 bits dynamic RA M module which assembled 36

Contextual Info: _u _ N AUER PHILIPS/DISCRETE • ObE D bbS3T31 00113bl T ■ BYV33F SERIES T-03-19 SCHOTTKY-BARRIER, ELECTRICALLY-ISOLATED DOUBLE RECTIFIER DIODES High-efficiency schottky-barrier double rectifier diodes in SOT-186 full-pack plastic envelopes,

Contextual Info: %EDl EDI8M1664C50/60/70/85/100 Megabit SRAM Module, JEDEC Pinout 64Kx16 Static RAM CMOS, Module Features The EDI8M1664C is a high speed 64Kx16 CMOS Static RAM Module consisting of four 4 32Kx8 CMOS Static RAMs in leadless chip carriers, surface mounted onto a

ITT transistoren

Abstract: nf schaltungen Schaltungen TDA4605-3 S910N diode sg 5 ts bus08a BD139 25EK ITT bzx 85
Contextual Info: S IE M E N S ICs für die Unterhaltungs­ elektronik SNTs Ausgabe 5.86 S IE M E N S ICs für die Unterhaltungselektronik SNTs Datenblätter der Typen TDA 4600-3, TDA 4601, TDA 4601 D, TDA 4605 Problemlos bestellen mit der SBS-Preis- und Lagerliste F ür Kunden in d er B undesrepublik D eutschlan d und Berlin W est .

A1HV

Abstract: OQ11 SLTC
Contextual Info: “H Y U N D A I 11 • M 11 W I I I H Y 5 1 1 8 2 6 0 J 5e r i e s 4 1 1 w n e us« n « A O o ä i i » .u w or* a o o M in o 1M X 16-bit CMOS nDRAM with 2CAS &WPB DESCRIPTION The HY5118260 is the new generation and fast dynamic RAM organized 1,048,576 x 16-bit. The HY5118260

Contextual Info: IBM0316409C IBM0316809C IBM0316169C IBM03164B9C Prelim inary 16M b S y n c h r o n o u s D R A M -D ie Revision E Features • M ultiple Burst Read w ith Single W rite O ption • High Perform ance: CL=3 : CL=2 / 3 ; CL=3 i: c. 3 • Units ; • A utom atic and C ontrolled Precharge C om m and

Contextual Info: PRELIMINARY I TECHNOLOGY. INC. 64Kx 16/18 SRAM +3.3V SUPPLY, PIPELINED AND SELECTABLE BURST MODE FEATURES • • • • • • • • • • • • • • • • • PIN ASSIGNMENT Top View Fast access times: 4 .5 ,5 ,6 ,7 ,8 and 9ns Fast OE# access time: 4.5,5 and 6ns

MT58LC256K18

Abstract: ct901
Contextual Info: ADVANCE 256K SYNCHRONOUS SRAM 256Kx 16/18 SRAM +3.3V SUPPLY, +2.5V I/O, PIPELINED AND SELECTABLE BURST MODE FEATURES • • • • • • • • • • • • • • • • • • PIN ASSIGNMENT Top View F ast access tim es: 4.5, 5, 5.5, 6 an d 7ns

SB6B

Contextual Info: HB56G232B/SB-6B/7B 2,097,152-word x 32-bit High Density Dynamic RAM Module HITACHI ADE-203-547A Z Rev. 1.0 Feb. 20,1996 Description The HB56G232 is a 2M x 32 dynamic RAM module, mounted 4 pieces o f 16-Mbit DRAM (HM5118160BJ) sealed in SOJ package. An outline o f the HB56G232 is 72-pin single in-line package. Therefore, the HB56G232 makes high

Contextual Info: M EDI8F32512C E D I S M x 3 2 SRAM Module ELECTOONC DOGNS. WC 512Kx32 Static RAM CMOS, High Speed Module F ea tu re s The EDI8F32512C is a high speed 16 megabit Static RAM module 512Kx32 bit CMOS Static organized as 512K words by 32 bits. This module is constructed

DQ14

Abstract: d022 dq24
Contextual Info: x32 Pinout Map for 64 and 72 pin ZIP Package Configurations 512KX32 256Kx32 128Kx32 64Kx32 PD3 PD3 PD0 PD0 PD2 PD0 DQ0 DQ0 DQ0 000 DQ0 DQ0 DQ0 DQ1 DQ1 DQ1 DQ1 DQ1 DQ1 DQ2 DQ2 DQ1 DQ2 DQ2 DQ2 0Q2 VSS PD0 DQ3 DQ3 DQ3 DQ3 DQ3 DQ3 DQ3 VCC VCC VCC VCC VCC VCC VCC

km418c256

Abstract: M418C KM418C256A
Contextual Info: CMOS DRAM KM418C256A/AL/ALL 256K x 18 Bit CMOS Dynamic RAM with Fast Page Mode FEATURES GENERAL DESCRIPTION • Performance range: The Samsung KM418C256A/AUALL is a CMOS high speed 262,144 bit x 18 Dynamic Random Access Memory. Its design is optimized for high performance

Contextual Info: IB M 11 M 16730C B 16M x 72 D R A M M O D U LE Features • 1 6 8 Pin J E D E C S tandard, 8 Byte D ual In-line M e m o ry M odule • Au contacts • 1 6 M x 7 2 F ast P a g e M o d e D IM M • System P erform ance Benefits: • P erform ance: • O ptim ized for E C C applications

Contextual Info: HYM72V64C736AT8 64Mx72, 32Mx8 based, PC133 DESCRIPTION The HYM72V64C736AT8 H-Series are high speed 3.3-Volt synchronous dynamic RAM Modules composed of eigh­ teen 32Mx8 bit Synchronous DRAMs in 54-pin TSOPII, two 48-pin SOP Register Buffers, one 24-pin SOP PLL and 8-pin

Contextual Info: TMS28F008Axy,TMS28F800Axy 1048576 BY 8-B1T/524 288 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES • Organization . . . • 1 1 • 1048576 By 8 Bits 524288 By 16 Bits Array-Blocking Architecture - Two 8K-Byte Parameter Blocks - One 96K-Byte Main Block - Seven 128K-Byte Main Blocks

Contextual Info: ADVANCE m i c r o 512K x 16, 1 MEG x 8 BOOT BLOCK FLASH MEMORY n FLASH MEMORY MT28F800B3 FEATURES PIN ASSIGNMENT Top View • Eleven erase blocks: 16KB/8K-word boot block (protected) Two 8KB/4K-word parameter blocks Eight main memory blocks • 3V-only, dual-supply operation:

Contextual Info: SAMSUNG ELECTRONICS INC 42E ]> B 7Tb4142 G0110Ô5 1 I IS 16 K PRELIMINARY CMOS EEPROM KM29C010 128K/8 Bit CMOS Electrically Erasable PROM FEATURES GENERATION DESCRIPTION • Fast Read Access Time: 120ns • Single 5 Voltage Supply • 128 Byte Page W rite Operation

altera ep900

Abstract: EP900 74HC EP910 altera EP910 ep900-2 ep9003
Contextual Info: ALTERA 24E D CO R P • 05^5375 GOOllDD r r ^ «nom s 24-M A C R O C E LL EPLO t 7 I -^ -4 7 EP900 FEATURES GENERAL DESCRIPTION • • • • • • • The Altera EP900 is a pin-compatible version of the popular EP910 Erasable Programmable Logic Device EPLD . Available in 40-pin DIP and 44-pln

TDQ40

Contextual Info: SGRAM MODULE KMM966G512BQ P N KMM966G512BQ(P)N SGRAM SODIMM 512Kx64 SGRAM SODIMM based on 256Kx32,1K Refresh, 3.3V Synchronous Graphie RAMs FEATURES GENERAL DESCRIPTION • Performance Range Part NO. Max. Freq. (tee) I KMM966G512BQ(P)N-G8 125MHz (8ns) @CL=3

Contextual Info: EDI8F3232C W D I 32KX32 SRAM Module ELECTRONIC. DESIGNS, INC 32KX32Static RAM CHIOS, Hitfi Speed Module Features TTie EDI8F3232C is a high speed megabit Static RAM 32Kx32 bit CMOS Static module organized as 32Kx32. This module is constructed Random Access Memory

IT2205

Abstract: IBM0316809CT3-10 g618ac
Contextual Info: IBM0316409CIBM0316809C IBM0316169C 16Mbit S yn ch ro n o u s DRAM Features • High Performance: • Multiple Burst Read with Single Write Option CAS latency = 3 -10 -11 -12 -13 Units • Automatic and Controlled Precharge Command fcK Clock Frequency 100 91

Contextual Info: GOULD 4055916 GOUL D IN C / GOULD A M I SEMI CONDUCTOR 03 DIV D • 03E MDSSTlb 1 1494 DQ114TM 0^ TABLE OF CONTENTS SECTION 1: DESIGN INFORMATION 1.1 CHOOSING AN ARRAY. 1-5 1.1.1 Determining Gate Count. 1-6

M5M4V4260CTP-7

Contextual Info: MITSUBISHI LSIs M5M4V4260CTP-6,-7,-6S,-7S FAST PAGE MODE 4194304-BIT 262144-WORD BY 16-BIT DYNAMIC RAM DESCRIPTION PIN CONFIGURATION (TOP VIEW) This is a family of 262144-word by 16-bit dynamic RAMs, fabricated with the high performance CMOS process, and Is ideal

A733B

Abstract: 3ac22 LM16 lcd QNDI02 GP021 PROJECT AT6 A1033B AH3R 3AA18 L8400F
Contextual Info: 8 U10A HA*{31:3 \ — nur 3 A 18 B17 A17 \ H/4T5 \ HAff6 \ HDfO HDfft H P *2 y y / HPg3 HD?4 HD?5 HD?6 A2Q — HP» y y y y y y D?3 B19 tHAff 7 C ?Q A? > HP#f63:0j U10B HD?9 A?4 ma D?4 -B24. _A1S HD? 11 HD?12 HD? 13 y y / H D ? 14 y H P g lj Hb? i6 HP? i7