HCT11 Search Results

IC 74HC112

Abstract: 74HC112
Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54/74HC112, CD54/HCT112 Data sheet acquired from Harris Semiconductor SCHS141A Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised May 2000

Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, HCT112, HCT112 Data sheet acquired from Harris Semiconductor SCHS141F Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised May 2003

CD54

Abstract: CD54HC11 CD54HC11F3A CD54HCT11 CD54HCT11F3A CD74HC11 CD74HCT11 HC11
Contextual Info: [ /Title CD54 HCT11 , CD74 HC11, CD74 HCT11 /Subject (High CD54HC11, CD74HC11, HCT11, HCT11 Data sheet acquired from Harris Semiconductor SCHS273C High-Speed CMOS Logic Triple 3-Input AND Gate August 1997 - Revised May 2003 Features Description

Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, HCT112, HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003

Contextual Info: 74HC/HCT11 T R IPLE 3-INPUT A N D GATE FEATURES T Y P IC A L • Output capability: standard • I q £ category: SSI SYMBOL G EN ERA L DESCRIPTION tp H iy tPLH propagation delay nA, nB, nC to n Y C| input capacitance CPD power dissipation capacitance per gate

Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, HCT112, HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003

CD54

Abstract: CD54HC11 CD54HC11F3A CD54HCT11 CD54HCT11F3A CD74HC11 CD74HCT11 HC11
Contextual Info: [ /Title CD54 HCT11 , CD74 HC11, CD74 HCT11 /Subject (High CD54HC11, CD74HC11, HCT11, HCT11 Data sheet acquired from Harris Semiconductor SCHS273E High-Speed CMOS Logic Triple 3-Input AND Gate August 1997 - Revised September 2003 Features Description

Contextual Info: [ /Title CD54 HCT11 , CD74 HC11, CD74 HCT11 /Subject (High CD54HC11, CD74HC11, HCT11, HCT11 Data sheet acquired from Harris Semiconductor SCHS273E High-Speed CMOS Logic Triple 3-Input AND Gate August 1997 - Revised September 2003 Features Description

Contextual Info: [ /Title CD54 HCT11 , CD74 HC11, CD74 HCT11 /Subject (High CD54HC11, CD74HC11, HCT11, HCT11 Data sheet acquired from Harris Semiconductor SCHS273E High-Speed CMOS Logic Triple 3-Input AND Gate August 1997 - Revised September 2003 Features Description

Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, HCT112, HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003

Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, HCT112, HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003

CD54HC112

Abstract: CD54HC112F3A CD54HCT112 CD54HCT112F3A CD74HC112 CD74HCT112
Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, HCT112, HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003

IN74ACT112D

Abstract: IN74ACT112N
Contextual Info: TECHNICAL DATA IN74ACT112 Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The IN74ACT112 is identical in pinout to the LS/ALS112, HC/HCT112. The IN74ACT112 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs.

IN74AC11D

Abstract: 5540a IN74AC11N
Contextual Info: TECHNICAL DATA IN74AC11 Triple 3-Input AND Gate High-Performance Silicon-Gate CMOS The IN74AC11 is identical in pinout to the LS/ALS11, HC/HCT11. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS

Contextual Info: [ /Title CD54 HCT11 , CD74 HC11, CD74 HCT11 /Subject (High CD54HC11, CD74HC11, HCT11, HCT11 Data sheet acquired from Harris Semiconductor SCHS273D High-Speed CMOS Logic Triple 3-Input AND Gate August 1997 - Revised July 2003 Features Description

Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, HCT112, HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003

74HCT11

Abstract: 74hc11
Contextual Info: [ /Title CD54 HCT11 , CD74 HC11, CD74 HCT11 /Subject (High CD54/74HC11, CD54/HCT11 Data sheet acquired from Harris Semiconductor SCHS273A High Speed CMOS Logic Triple 3-Input AND Gate August 1997 - Revised May 2000 Features Description • Buffered Inputs

CD74HC112

Abstract: 74HCT 74LS CD74HC112E CD74HCT112
Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD74HC112, HCT112 Data sheet acquired from Harris Semiconductor SCHS141 Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 Features at VCC = 5V

KK74AC112

Abstract: KK74AC112D KK74AC112N
Contextual Info: TECHNICAL DATA KK74AC112 Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The KK74AC112 is identical in pinout to the LS/ALS112, HC/HCT112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs.

Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, HCT112, HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003

Contextual Info: [ /Title CD54 HCT11 , CD74 HC11, CD74 HCT11 /Subject (High CD54HC11, CD74HC11, HCT11, HCT11 Data sheet acquired from Harris Semiconductor SCHS273E High-Speed CMOS Logic Triple 3-Input AND Gate August 1997 - Revised September 2003 Features Description

Scans-052

Contextual Info: CD54HC112F3A, HCT112F3A June 1997 Dual J-K Flip-Flop with Set and Reset File Number 3774.1 Functional Diagram This device is fully compliant to the requirements of paragraph 1.2.1 of MIL-STD-883. The CD54HC/HCT112F3A utilizes silicon-gate CMOS technology to achieve operating speeds equivalent to LSTTL

IN74AC112

Abstract: IN74AC112D IN74AC112N
Contextual Info: TECHNICAL DATA IN74AC112 Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The IN74AC112 is identical in pinout to the LS/ALS112, HC/HCT112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS

Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, HCT112, HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003