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    CONN TRBLK 4

    Abstract: C0402X7R100-104K HEADER_1X3
    Text: Si 5 3 3 0 1 / 4 - E VB Si53301/4 E VALUATION B OARD U SER ’ S G U ID E Description EVB Features The Si53301/4-EVB is used for evaluation of the Si533xx family of low-jitter clock buffers/level translators. As shipped from the factory, this evaluation board has the Si53301 device installed. The entire


    Original     		PDF Si53301/4 Si53301/4-EVB Si533xx Si53301 Si53304 CONN TRBLK 4 C0402X7R100-104K HEADER_1X3

    Untitled

    Abstract: No abstract text available
    Text: Si5365 P I N - P ROGRAMMABLE P R E C I S I O N C LOCK M U LT IP L I E R Features      Not recommended for new  designs. For alternatives, see the Si533x family of products. Selectable output frequencies  ranging from 19.44 to 1050 MHz


    Original     		PDF Si5365 Si533x

    Untitled

    Abstract: No abstract text available
    Text: Si5367 µ P - P ROGRAMMABLE P RECISION C L O C K M ULTIPLIER Features      Not recommended for new  designs. For alternatives, see the Si533x family of products. Generates any frequency from  2 kHz to 945 MHz and select frequencies to 1.4 GHz from an 


    Original     		PDF Si5367 Si533x

    Untitled

    Abstract: No abstract text available
    Text: AN408 TERMINATION O P T I O N S FOR A NY - F R E QUE N C Y, A N Y - O UTPUT C LOCK G ENERATORS A N D C LOCK B UFFERS 1. Introduction This application note provides termination recommendations for connecting input and output clock signals to the Si533x and Si5356/55 family of timing ICs and is not applicable to any other Silicon Labs devices.


    Original     		PDF AN408 Si533x Si5356/55

    Untitled

    Abstract: No abstract text available
    Text: Si5322 P I N - P ROGRAMMABLE P R E C I S I O N C LOCK M U LT IP L I E R Features      Not recommended for new  designs. For alternatives, see the Si533x family of products. Selectable output frequencies  ranging from 19.44 to 1050 MHz


    Original     		PDF Si5322 Si533x

    AN360

    Abstract: crystal 26 Mhz AB10-25MHZ-E20-T Si533x NX5032GA-25MHZ ECS-250-8-36CKM TSX-3225 EPSON 25Mhz datasheet crystal TSX-3225 CL1112
    Text: AN360 C R YS TA L S ELECTION G UIDE FOR Si533 X A N D Si5355/56 D EVICES 1. Introduction This application note provides general guidelines for the selection and use of crystals with the Si533x and Si5355/56 family of any-frequency, any-output clock generators and zero-delay buffers. Many of these devices can


    Original     		PDF AN360 Si533 Si5355/56 Si533x Si533x/5x AN360 crystal 26 Mhz AB10-25MHZ-E20-T NX5032GA-25MHZ ECS-250-8-36CKM TSX-3225 EPSON 25Mhz datasheet crystal TSX-3225 CL1112

    Untitled

    Abstract: No abstract text available
    Text: Si5322 P I N - P ROGRAMMABLE P R E C I S I O N C LOCK M U LT IP L I E R Features      Not recommended for new  designs. For alternatives, see the Si533x family of products. Selectable output frequencies  ranging from 19.44 to 1050 MHz


    Original     		PDF Si5322 Si533x

    0011b

    Abstract: No abstract text available
    Text: Si5367 µ P - P ROGRAMMABLE P RECISION C L O C K M ULTIPLIER Features      Not recommended for new  designs. For alternatives, see the Si533x family of products. Generates any frequency from  2 kHz to 945 MHz and select frequencies to 1.4 GHz from an 


    Original     		PDF Si5367 Si533x 0011b

    Si533x

    Abstract: AN408 AN4087 50 Ohm Termination Texas independent termination "50 Ohm" si5330 data sheet si5338 Si5356 AN360 Si5334
    Text: AN408 TERMINATION O P T I O N S FOR A NY - F R E QUE N C Y, A N Y - O UTPUT C LOCK G ENERATORS A N D C LOCK B UFFERS 1. Introduction This application note provides termination recommendations for connecting input and output clock signals to the Si533x and Si5356/55 family of timing ICs and is not applicable to any other Silicon Labs devices.


    Original     		PDF AN408 Si533x Si5356/55 AN408 AN4087 50 Ohm Termination Texas independent termination "50 Ohm" si5330 data sheet si5338 Si5356 AN360 Si5334

    Si53xx-RM

    Abstract: No abstract text available
    Text: Si5365 P I N - P ROGRAMMABLE P R E C I S I O N C LOCK M U LT IP L I E R Features      Not recommended for new  designs. For alternatives, see the Si533x family of products. Selectable output frequencies  ranging from 19.44 to 1050 MHz


    Original     		PDF Si5365 Si533x Si53xx-RM

    si514

    Abstract: SI510
    Text: AN765 T HERMAL A NALYSIS OF S I L I C O N L ABS T I M I N G D EVICES 1. Introduction The junction temperature of semiconductor devices affects reliability and performance of Integrated Circuits ICs , including timing devices. This application note provides the following:


    Original     		PDF AN765 si514 SI510

    what is slew rate

    Abstract: No abstract text available
    Text: AN766 U NDERSTANDING A N D O PTIMIZING C L O C K B UFFER ’ S A D D IT I V E J ITTER P E R F OR MA N C E 1. Introduction This application note details the various contributions to a clock distribution’s buffer’s additive phase noise performance and how to optimize performance without increasing costs.


    Original     		PDF AN766 what is slew rate

    Si5338

    Abstract: Si533x SI5338A Si5338C SI5334C
    Text: Industry’s First Any-Rate, Any-Output Clock Generators One Stop for Customers’ Timing Needs Any-Rate Precision Clocks Single/Dual/Quad/Any-Rate Any-Rate Frequency XO/VCXOs Crystal-Less Oscillators Any-Rate Clock Generators/Buffers Broad portfolio based on proprietary DSPLLTM and MultiSynth technology:


    Original     		PDF 24-QFN Si5334 OC-3/12, Si5334A Si5338 Si533x SI5338A Si5338C SI5334C

    si5332

    Abstract: SMA103A qfn 3X3 land pattern 5310A
    Text: Si53322 1:2 L OW - J I T T E R LVPECL C L O C K B UFFER Features  2 LVPECL outputs   Ultra-low additive jitter: 45 fs rms   Wide frequency range: dc to 1250 MHz   Universal input stage accepts  differential or LVCMOS clock VDD: 2.5 / 3.3 V


    Original     		PDF Si53322 16-QFN si5332 SMA103A qfn 3X3 land pattern 5310A

    capacitor rse 104

    Abstract: Si5356B-A00322-GM SI5356B
    Text: Si5356B * I 2C P ROGRAMMABLE , A NY - F R E Q U E N C Y 1 – 2 0 0 M H Z , Q UAD F R E Q U E N C Y 8-O UTPUT C LOCK G ENERATOR Features          Generates any frequency from 1 to  200 MHz on each of the 4 output banks Eight CMOS clock outputs


    Original     		PDF Si5356B capacitor rse 104 Si5356B-A00322-GM

    Untitled

    Abstract: No abstract text available
    Text: Si53302 1 : 1 0 L OW J I T T E R U NIVERSAL B U FF E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX Features Ordering Information: See page 29. Applications 34 37 35 36 38 39 40 41 The Si53302 is an ultra low jitter ten output differential buffer with pin-selectable


    Original     		PDF Si53302

    Si53304

    Abstract: No abstract text available
    Text: Si53304 1:6 L OW J I T T E R U NIVERSAL B U F F E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX A N D I NDIVIDUAL OE Features         6 differential or 12 LVCMOS outputs  Ultra-low additive jitter: 100 fs rms  Wide frequency range: 1 to 725 MHz


    Original     		PDF Si53304 32-QFN

    Untitled

    Abstract: No abstract text available
    Text: Si5356A I 2C P ROGRAMMABLE , A NY - F R E Q U E N C Y 1 – 2 0 0 M H Z , Q UAD F R E Q U E N C Y 8-O UTPUT C LOCK G ENERATOR Features          Generates any frequency from 1 to  200 MHz on each of the 4 output banks Programmable frequency configuration 


    Original     		PDF Si5356A

    Si5338C

    Abstract: Si5338 AN562 JESD78 SSTL-18 UM10204 3G-SDI serializer Si5338A SDI SERIALIZER Si5338s
    Text: Si5338 I 2 C - P R O GRA MM A B LE A NY - F R E Q U E N C Y, A NY - O UTPUT Q UAD C LOCK G ENERATOR Features Applications CLK0B VDDO0 SDA 22 21 20 19 18 CLK1A IN2 2 17 CLK1B IN3 3 16 VDDO1 GND GND Pad IN4 4 15 VDDO2 IN5 5      Any-frequency clock conversion


    Original     		PDF Si5338 24-QFN 45consequential Si5338C Si5338 AN562 JESD78 SSTL-18 UM10204 3G-SDI serializer Si5338A SDI SERIALIZER Si5338s

    Si5338

    Abstract: Si533x si5338b stk 282 STK 290 010 stk 2250 stk 282 270 BY165 si5330 data sheet AN408
    Text: Si5338 I 2 C - P R O G R A M M A B LE A N Y - F R E Q U E N C Y, A N Y -O UTPU T Q U A D C L OC K G E N E R A T O R Features Applications CLK0B VDDO0 SDA 22 21 20 19 18 CLK1A IN2 2 17 CLK1B IN3 3 16 VDDO1 GND GND Pad IN4 4 15 VDDO2 IN5 5     Any-frequency clock conversion


    Original     		PDF Si5338 24-QFN Si5338 Si533x si5338b stk 282 STK 290 010 stk 2250 stk 282 270 BY165 si5330 data sheet AN408

    Untitled

    Abstract: No abstract text available
    Text: Si5338 I 2 C - P R O GRA MM A B LE A NY - F R E Q U E N C Y, A NY - O UTPUT Q UAD C LOCK G ENERATOR Features Applications CLK0B VDDO0 SDA 22 21 20 19 18 CLK1A IN2 2 17 CLK1B IN3 3 16 VDDO1 GND GND Pad IN4 4 15 VDDO2 IN5 5      Any-frequency clock conversion


    Original     		PDF Si5338

    Untitled

    Abstract: No abstract text available
    Text: Si53304 1:6 L OW J I T T E R U NIVERSAL B U F F E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX A N D I NDIVIDUAL OE Features         6 differential or 12 LVCMOS outputs  Ultra-low additive jitter: 45 fs rms Wide frequency range: 1 to 725 MHz 


    Original     		PDF Si53304

    cross reference guide

    Abstract: Silabs SI53302-B-GM
    Text: Si53302 1 : 1 0 L OW J I T T E R U NIVERSAL B U FF E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX Features         10 differential or 20 LVCMOS outputs Ultra-low additive jitter: 45 fs rms Wide frequency range: 1 to 725 MHz  Any-format input with pin selectable


    Original     		PDF Si53302 44-QFN cross reference guide Silabs SI53302-B-GM

    land pattern for TSsOP 16

    Abstract: CDCLVC1108 Si53365 si5336
    Text: Si53365 1:8 L O W J I T T E R CMOS C LOCK B U FF E R <200 MH Z Features       8 LVCMOS outputs  Ultra-low additive jitter: 150 fs rms  Wide frequency range: 1 to 200 MHz  Asynchronous output enable Low output-output skew: <150 ps


    Original     		PDF Si53365 CDCLVC1108 16-TSSOP land pattern for TSsOP 16 si5336