SMA103A Search Results

si5332

Abstract: SMA103A qfn 3X3 land pattern 5310A
Contextual Info: Si53322 1:2 L OW - J I T T E R LVPECL C L O C K B UFFER Features  2 LVPECL outputs   Ultra-low additive jitter: 45 fs rms   Wide frequency range: dc to 1250 MHz   Universal input stage accepts  differential or LVCMOS clock VDD: 2.5 / 3.3 V

Si53308

Abstract: Si533x
Contextual Info: Si53308 D U A L 1 : 3 L O W - J I T T E R B UFFER / L EVEL T RANSLATOR Features Ordering Information: See page 28. Storage Telecom  Industrial  Servers  Backplane clock distribution Q2 Q3 Q3 Q4 Q4 26 25 27 28 29 30 Vref Generator DIVA SFOUTA[1] SFOUTA[0]

Contextual Info: Si53302 1 : 1 0 L OW J I T T E R U NIVERSAL B U FF E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX Features Ordering Information: See page 29. Applications 34 37 35 36 38 39 40 41 The Si53302 is an ultra low jitter ten output differential buffer with pin-selectable

Contextual Info: Si53304 1:6 L OW J I T T E R U NIVERSAL B U F F E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX A N D I NDIVIDUAL OE Features         6 differential or 12 LVCMOS outputs  Ultra-low additive jitter: 45 fs rms Wide frequency range: 1 to 725 MHz 

cross reference guide

Abstract: Silabs SI53302-B-GM
Contextual Info: Si53302 1 : 1 0 L OW J I T T E R U NIVERSAL B U FF E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX Features         10 differential or 20 LVCMOS outputs Ultra-low additive jitter: 45 fs rms Wide frequency range: 1 to 725 MHz  Any-format input with pin selectable

Contextual Info: Si53306 1 : 4 L O W - J ITTER U N I V E R S A L B U F F E R / L E V E L T R A N S L A T O R Features Independent VDD and VDDO : 1.8/2.5/3.3 V 1.2/1.5 V LVCMOS output support Selectable LVCMOS drive strength to tailor jitter and EMI performance Small size: 16-QFN 3 mm x 3 mm

Contextual Info: Si53314 1:6 L O W J I T T E R U NIVE RS AL B UFFER /L EVEL T RANSL ATOR W I T H 2 : 1 I NPUT M UX AND I N D I V I D U A L OE <1.25 GH Z Features    Ordering Information: See page 27. Applications Storage Telecom  Industrial  Servers  Backplane clock distribution

Si53340-B-GM

Abstract: si53340 SMA103A 5310A
Contextual Info: Si53340 1:4 L O W - J I T T E R LV DS C LO C K B U F F E R WITH 2:1 INPUT MUX Features      4 LVDS outputs  Ultra-low additive jitter: 45 fs rms  Wide frequency range: dc to 1250 MHz  2:1 input mux  Universal input stage accepts

536FS

Contextual Info: Si53301 1:6 L OW J I T T E R U NIVERSAL B U F F E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX Features Ordering Information: See page 28. Storage Telecom  Industrial  Servers  Backplane clock distribution Q3 Q4 Q4 29 28 27 26 25 Functional Block Diagram

5310A

Contextual Info: Si53323 1:4 L O W - J I T T E R LV PECL C L O C K B U F F E R WI TH 2 : 1 I N P U T M UX Features      4 LVPECL outputs  Ultra-low additive jitter: 45 fs rms  Wide frequency range: dc to 1250 MHz  2:1 input mux  Universal input stage accepts

Contextual Info: Si53301 1:6 L OW J I T T E R U NIVERSAL B U F F E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX Features Storage Telecom  Industrial  Servers  Backplane clock distribution Q3 Q4 Q4 30 29 28 27 26 25 1 24 DIVB SFOUTA[1] 2 23 SFOUTB[1] SFOUTA[0] 3 Q0

Si53306

Abstract: Si53306-B-GM 5310A
Contextual Info: Si53306 1 : 4 L O W - J ITTE R U N I V E R S A L B U F F E R / L E V E L T R A N S L A T O R Features  4 differential or 8 LVCMOS outputs  Ultra-low additive jitter: 45 fs rms  Wide frequency range: 1 to 725 MHz   Any-format input with pin selectable