74LS08 fan-in
Abstract: 74LS398 74LS273 74LS14 Hex Inverter definition MC74F579 74LS181 74ls795 74LS299 Decade Up/Down counter 3 State ttl buffer 74LS245
Text: Selection Information FAST/LS TTL 1 Circuit Characteristics 2 Design Considerations, Testing and Applications Assistance Form 3 FAST Data Sheets 4 LS Data Sheets 5 Reliability Data 6 Package Information Including Surface Mount 7 FAST AND LS TTL DATA CLASSIFICATION
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81LS96)
81LS97)
81LS98)
74LS08 fan-in
74LS398
74LS273
74LS14 Hex Inverter definition
MC74F579
74LS181
74ls795
74LS299
Decade Up/Down counter 3 State
ttl buffer 74LS245
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FZH115B
Abstract: fzh261 FZK105 FZH131 FZJ111 FZH115 FZH205 Multiplexer IC 74151 FZH265B 74LS104
Text: Digital I.C.s, 74INTEGRATED CIRCUITS DIGITAL TTL, 74LS & 74HC Series Quad 2-input NAND gate Quad 2-input NAND gate, open collector Quad 2-input NOR gate Quad 2-input NOR gate, open collector Hex inverter Hex inverter, O/C collector Hex inverter, Buffer 30V O/P
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74INTEGRATED
Line-to-10
150ns
16-DIL
150ns
18-pin
250ns
300ns
FZH115B
fzh261
FZK105
FZH131
FZJ111
FZH115
FZH205
Multiplexer IC 74151
FZH265B
74LS104
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74LS76A
Abstract: SN54/74LS76A datasheet 74ls76a truth table NOT gate 74
Text: SN54/74LS76A DUAL JK FLIP-FLOP WITH SET AND CLEAR The SN54/ 74LS76A offers individual J, K, Clock Pulse, Direct Set and Direct Clear inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The Logic Level
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SN54/74LS76A
74LS76A
SN54/74LS76A
datasheet 74ls76a
truth table NOT gate 74
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74LS76
Abstract: 74LS76A datasheet 74ls76a SN54/74LS76A
Text: SN54/74LS76A DUAL JK FLIP-FLOP WITH SET AND CLEAR The SN54 / 74LS76A offers individual J, K, Clock Pulse, Direct Set and Direct Clear inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The Logic Level
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SN54/74LS76A
74LS76A
74LS76
datasheet 74ls76a
SN54/74LS76A
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74LS82
Abstract: 74LS176 74LS94 74LS286 74ls150 74LS177 74LS116 74ls198 7400 TTL 74ls521
Text: GOULD 4055916 GOULD SEMICONDUCTOR SEMICONDUCTOR DIV DIV 03E D | 03E MDSSTlb 09920 D UCICmEU T-4 3I-V 7400 TTL Cells •> GOULD CM OS Gate Array and Standard Cell Library Electronics Features General Description • Over 200 functions available. 7400 TTL Cells, a member of Gould’s EXPERT ASIC
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74LS
Abstract: 74LS765 N74LS765A N74LS765N PLCC-44
Text: 74LS765 Signetics DRAM Controller DRAM Dual-Ported Controller Preliminary Specification Logic Products FEATURES • Allows two microprocessors to access the same bank of DRAM • Replaces 25 TTL devices to perform arbitration, signal timing, multiplexing, and refresh
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LS764
30MHz
74LS765
74LS
N74LS765A
N74LS765N
PLCC-44
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74LS764
Abstract: logic diagram and symbol of DRAM 74LS N74LS764A N74LS764N PLCC-44 18-BlT LS764
Text: 74LS764 Signetics DRAM Controller DRAM Dual-Ported Controller Product Specification Logic Products FEATURES • Allows two microprocessors to access the same bank of DRAM • Replaces 25 TTL devices to perform arbitration, signal timing, multiplexing, and refresh
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74LS764
18-blt
30MHz
74LS764
IN916,
IN3064,
500ns
logic diagram and symbol of DRAM
74LS
N74LS764A
N74LS764N
PLCC-44
LS764
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74LS764
Abstract: LS764
Text: 74LS764 Signetics DRAM Controller DRAM Dual-Ported Controller Product Specification Logic Products FEATURES • Allows two microprocessors to access the same bank of DRAM • Replaces 25 TTL devices to perform arbitration, signal timing, multiplexing, and refresh
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74LS764
18-blt
30MHz
215mA
PLCC-44
WF06450S
IN916,
IN3064,
74LS764
LS764
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LS764
Abstract: A12E
Text: 74LS765 Signelics DRAM Controller DRAM Dual-Ported Controller Preliminary Specification Logic Products FEATURES • Allows two microprocessors to access the same bank of DRAM • Replaces 25 TTL devices to perform arbitration, signal timing, multiplexing, and refresh
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74LS765
LS764
30MHz
215mA
PLCC-44
N74LS765N*
N74LS765A*
6002230S
A12E
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74LS
Abstract: 74LS765 N74LS765A N74LS765N PLCC-44
Text: 74LS765 Signetìcs DRAM Controller DRAM Dual-Ported Controller Preliminary Specification Logic Products FEATURES • Allows two microprocessors to access the same bank of DRAM • Replaces 25 TTL devices to perform arbitration, signal timing, multiplexing, and refresh
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LS764
30MHz
74LS765
A15Q3
74LS
N74LS765A
N74LS765N
PLCC-44
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74ls
Abstract: N74LS764N
Text: Signelics 74LS764 DRAM Controller DRAM Dual-Ported Controller Product Specification Logic Products FEATURES • Allows two microprocessors to access the same bank of DRAM TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT TOTAL • Replaces 25 TTL devices to
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74LS764
18-bit
30MHz
215mA
PLCC-44
N74LS764N
N74LS764A
500ns
74ls
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A1266
Abstract: 16KX8 74LS 74LS764 N74LS764A N74LS764N PLCC-44
Text: 74LS764 S ignetics DRAM Controller DRAM Dual-Ported Controller Product Specification Logic Products FEATURES • Allows two microprocessors to access the same bank of DRAM • Replaces 25 TTL devices to perform arbitration, signal timing, multiplexing, and refresh
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18-bit
30MHz
74LS764
discret64
IN916,
IN3064,
500ns
A1266
16KX8
74LS
N74LS764A
N74LS764N
PLCC-44
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transistor cross reference
Abstract: MPT3N40 Westinghouse SCR handbook LT 8224 ZENER DIODE sje389 N9602N npn transistor RCA 467 TFK 7 segment displays PUT 2N6027 delco 466
Text: C K TBD DOLLY LIST LOGO LIST SAFETY & RELIABLTY TEK PN SYSTEM II DIGITAL IC's MEMORIES. MOS. CM OS.ECL. TTL MICROPROCESSOR SPECIAL FUNCTION IC's DIGITAL / LINEAR ARRAYS LINEAR IC'S (PURCH) TEK-MADE IC’s 3 IC's INDEX (COLORED PGS) INCL PRGMD. SCRND.ETC
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logic ic 74LS76 pin diagram
Abstract: j-k flip flop 74ls76 IC 74LS76
Text: LS TTL DN74LS Series DN74LS76 D N 74LS76 D ^ 74^ 7^ Dual J-K F lip -F lo p s with S e t and Reset • Description P -2 D N 7 4 L S 7 6 contains tw o negative-edge triggered J-K flip-flop circuits, each w ith independent clock-C P, J, K, and directcoupled set and reset input terminals.
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DN74LS
DN74LS76
74LS76
16-pin
logic ic 74LS76 pin diagram
j-k flip flop 74ls76
IC 74LS76
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dm8130
Abstract: 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76
Text: 19 7 6 N atio n al S e m ico n d u cto r C o rp . p 1 ? I m • ' % TTL Data Book D EV IC E MIL i 2502 2503 2504 5400 54H00 54L00 54LS00 5401 54H01 54L01 54LS01 5402 54L02 54LS02 5403 54L03 54LS03 5404 54H04 54L04 54LS04 5405 54H05 54L05 54LS05 5406 5407 5408
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54H00
54L00
54LS00
54H01
54L01
54LS01
54L02
54LS02
54L03
54LS03
dm8130
54175
DM74367
KS 2102
7486 ic truth table
signetics 2502
ci 8602 gn block diagram
ci 8602 gn
74s281
DM74LS76
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TTL 74ls74
Abstract: 74ls74 CI 7473 TTL 7474 7476 JK ttl 7474 14 PIN Jk 7476 7474 PIN DIAGRAM pin diagram 7474 7474 16 PIN
Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED D55 9020 D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 5 ui 9 D UJ -=pi (3 J Q 2 — J SD 0 CP Z o (3 4 K Ä Co “LT in > </> O a 3 -0 K Co ° I- 3 a. I- 3 O 4-0 Co ? 15 D61 54/7474, 54H/74H74,
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54S/74S109,
54LS/74LS109
54H/74H74,
54S/74S74,
54LS/74LS74
54H/74H73,
54H/74H73
54H/74H103
54S/74S113
54LS/74LS113
TTL 74ls74
74ls74
CI 7473
TTL 7474
7476 JK
ttl 7474 14 PIN
Jk 7476
7474 PIN DIAGRAM
pin diagram 7474
7474 16 PIN
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CI 7474
Abstract: CI 7473 ci 7476 7474 D latch CI 74LS76 CI 74107 TTL 74ls76 fairchild 9024 ci 74LS74 74ls107
Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED D55 9020 D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 ui 9 D UJ 5 -=pi (3 J Q 2 — J SD 0 CP Z o (3 11 4 K Ä 0 Co “LT in > _6 12 CP 3 -0 14 K Co ° 7 o-i- CP 13 —c K Cd °
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54S/74S109,
54LS/74LS109
54H/74H74,
54S/74S74,
54LS/74LS74
54H/74H73,
54LS/74LS279
93L14
54LS/74LS196
54LS/74LS197
CI 7474
CI 7473
ci 7476
7474 D latch
CI 74LS76
CI 74107
TTL 74ls76
fairchild 9024
ci 74LS74
74ls107
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TTL 74ls74
Abstract: 7474 14 PIN 74ls76 7476 ttl ttl 74ls109 74LS107 74LS73 74ls74 TTL 74ls76 74LS109
Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL M A S T E R /S LA V E E D G E -T R IG G E R E D D55 9020 D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 ui 9 D UJ 5 -=pi J Q (3 CP o K Z 2 — J SD 0 _6 Co (3 “LT in > z o Q J CP I- 3 a. 3 O So J - Ö K 4-0
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54S/74S109,
54LS/74LS109
54H/74H74,
54S/74S74,
54LS/74LS74
54H/74H73,
54L15
TTL 74ls74
7474 14 PIN
74ls76
7476 ttl
ttl 74ls109
74LS107
74LS73
74ls74
TTL 74ls76
74LS109
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7475 D latch
Abstract: D146 D147 ci 7475 rs latch 74LS109 74LS78 74LS107 74LS114 7475 data latch
Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D82 54LS/74LS78 D81 54LS/74LS541 V cc |S5| RSj FSI F7| F»l FS1 j b j j j F5I Fä| F I j j j SD SD J Q J C CP Q — e Q 5— 9 CP K >— 12 Q K CD CD LlI l i l LiJ L il L iT I U LzJ Ll I ü ü bsJ QNO 9 3 4 li
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54LS/74LS541
54LS/74LS78
54LS/74LS168,
54LS/74LS169
54LS/74LS490
54LS/74LS373
54LS/74LS374
54LS/74LS256
54LS/74LS279
93L14
7475 D latch
D146
D147
ci 7475
rs latch
74LS109
74LS78
74LS107
74LS114
7475 data latch
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NE74LS
Abstract: 74ls76
Text: Signetìcs 74LS765 DRAM Controller DRAM Dual-Ported Controller Preliminary Specification Logic Products FEATURES TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT TOTAL 74LS765 45ns 215mA • Allows two microprocessors to access the same bank of DRAM
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74LS765
LS764
30MHz
74LS765
215mA
PLCC-44
N74LS765N*
N74LS765A*
C007460S
NE74LS
74ls76
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74LS76A
Abstract: No abstract text available
Text: M MOTOROLA SN54/74LS76A DUAL JK FLIP-FLOP WITH SET AND CLEAR The S N 54/74LS 76A offers individual J, K, Clock Pulse, Direct Set and Di rect Clear inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The Logic Level
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SN54/74LS76A
54/74LS
74LS76A
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74ls76a
Abstract: 74LS76AD
Text: M M O TO R O LA SNS4/74LS76A D E S C R I P T I O N — The S N 5 4 L S /7 4 L S 7 6 A offers individual J. K, Clock Pulse, D irect S et and Direct Clear inputs. These dual flip-flops are designed so that w h e n the clock goes HIGH, the inputs B re enabled and
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SNS4/74LS76A
74ls76a
74LS76AD
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74hct76
Abstract: Jk 74ls76 pin out HC76 74HC76 LS 74LS76 GD54/74HCT76 74HC GD54HC76 GD74HC76 74HC LOGIC PINOUT
Text: GD54/74HC76, GD54/74HCT76 DUAL J-K FLIP-FLOPS WITH PRESET & CLEAR General Description These devices are identical in pinout to the 54/74LS76. These flip-flops are edge sensitive to the clock input and change state on the negative go ing transition of the clock pulse. Each flip-flop has
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GD54/74HC76,
GD54/74HCT76
54/74LS76.
GD54/74HC/HC76,
74hct76
Jk 74ls76 pin out
HC76
74HC76
LS 74LS76
GD54/74HCT76
74HC
GD54HC76
GD74HC76
74HC LOGIC PINOUT
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MH1SS1
Abstract: TESLA mh 7400 MH 7404 mh 7400 tesla cdb 838 tda 7851 L 741PC TDB0124DP tda 4100 TDA 7851 A
Text: m ö lk ^ o e le l-c te n a n il-c Information Applikation RGW Typenübersicht Vergleich Teil 2: RGW M iM U Z A U l KÉD lnrüÖC=SraO Information Applikation HEFT 50 RGW Typenübersicht + Vergleich Teil 2: RGW wob Halbleiterwerk Frankfurt /oder bt r iab im v«b kombinat mikrootektronik
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