ULTRA38000 Search Results

Contextual Info: PRESS RELEASE CYPRESS BROADENS Warp SOFTWARE SUPPORT Offers Support for LPM and Ultra38000 FPGAs, Introduces Low-Cost Simulation Product SAN JOSE, Calif., December 16, 1996 - In a move geared to extend its leadership in low-cost, high-quality programmable logic design tools, Cypress Semiconductor Corp.

n20s

Abstract: A144 BG256 IEEE1164 Military Plastic pASIC 3 Family 256
Contextual Info: 3T PRELIMINARY CYPRESS Ultra38007 UltraLogic Very High Speed 7K Gate CMOS FPGA Features — Minimum Iol and Ioh 24 mA Flexible logic cell architecture — Wide fan-in up to 16 input gates — Multiple outputs in each cell — Very low cell propagation delay

loadable counter

Contextual Info: ADVANCED INFORMATION m .7 Ultra38016 C Y P R E S S UltraLogic Very High Speed 16K Gate CMOS FPGA Features • Very high speed — Loadable counter frequencies greater than 185 MHz — Chip-to-chip operating frequencies up to 135 MHz — Input + logic cell + output delays

Contextual Info: CYPRESS Features • Very high speed — Loadable counter frequencies greater than 185 MHz — Chip-to-chip operating frequencies up to 135 MHz — Input + logic cell + output delays under 5.5 ns • Unparalleled FPGA performance for counters, data path, state machines,

loadable counter

Contextual Info: CYPRESS Features • Full 3.3V operation • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz — Input + logic cell + output delays under 7 ns • Unparalleled FPGA performance for counters, data path, state machines,

Contextual Info: = / CYPRESS ADVANCED INFORMATION Ultra338005 UltraLogic Very High Speed 5K Gate 3.3V CMOS FPGA Features • Fall 3.3V operation • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz

AAAG 6 pin ic

Abstract: n208
Contextual Info: CYPRESS Features PRELIMINARY UltraLogic Very High Speed 7K Gate CMOS FPGA — Minimum Iol and Ioh ° f 24 mA • Flexible logic cell architecture — Wide fan-in up to 16 input gates — Multiple outputs in each cell — Very low cell propagation delay

Contextual Info: CYPRESS Features • Very high speed — Loadable counter frequencies greater than 185 MHz — Chip-to-chip operating frequencies up to 135 MHz — Input + logic cell + output delays under 5.5 ns • Unparalleled FPGA performance for counters, data path, state machines,

architecture of cypress FLASH370 device

Abstract: cypress FLASH370 programming architecture of cypress FLASH370
Contextual Info: PRESS RELEASE CYPRESS ADDS NEW SYNTHESIS CAPABILITY TO $99 WARP2 Leading VHDL Programming Tool Now Supports All Cypress PLDs and CPLDs SAN JOSE, Calif., April 22, 1996 - Cypress Semiconductor Corp. today introduced Release 4 of its highly popular, $99 VHDL-based Warp2

Contextual Info: F# CYPRESS Features • Full 3 J V operation • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz — Input + logic cell + output delays under 7 ns • Unparalleled FPGA performance for

Contextual Info: f? CYPRESS Features • Very high speed — Loadable counter frequencies greater than 185 MHz — Chip-to-chip operating frequencies up to 135 MHz — Input + logic cell + output delays under 5.5 ns • U nparalleled FPGA performance for counters, data path, state machines,

architecture of cypress FLASH370 device

Abstract: FLASH370
Contextual Info: PRESS RELEASE CYPRESS ADDS NEW SYNTHESIS CAPABILITY, FPGA SUPPORT TO $99 WARP2 Leading VHDL Programming Tool Now Supports All Cypress PLDs, CPLDs, and FPGAs SAN JOSE, Calif., April 22, 1996 - Cypress Semiconductor Corp. today introduced Release 4 of its highly popular, $99 VHDL-based Warp2

7C380

Contextual Info: 7c3803: October 12, 1995 Revised: October 24, 1995 Ultra38003 ADVANCED INFORMATION UltraLogict Very High Speed 3K Gate CMOS FPGA D Robust routing resources Features D Very high speed D D D D D D Ċ Loadable counter frequencies greater than 185 MHz Ċ ChipĆtoĆchip operating frequencies

CISC AND RISC

Abstract: 7C380
Contextual Info: 7c3820: October 11, 1995 Revision: October 25, 1995 ADVANCED INFORMATION Ultra38020 UltraLogict Very High Speed 20K Gate CMOS FPGA Features D Very high speed D D D D D D Ċ Loadable counter frequencies greater than 185 MHz Ċ ChipĆtoĆchip operating frequencies

Contextual Info: W / CYPRESS ADVANCED INFORMATION Ultra38003 UltraLogic Very High Speed 3K Gate CMOS FPGA Features • Very high speed — Loadable counter frequencies greater than 185 MHz — Chip-to-chip operating frequencies up to 135 MHz — Input + logic cell + output delays

Contextual Info: CYPRESS Features • Very high speed — Loadable counter frequencies greater than 1SS MHz — Chip-to-chip operating frequencies up to 135 MHz — Input + logic cell + output delays under 5.5 ns • Unparalleled FPGA performance for counters, data path, state machines,

84-PIN

Abstract: Ultra38005
Contextual Info: CYPRESS Features • Very high speed — Loadable counter frequencies greater than 185 MHz — Chip-to-chip operating frequencies up to 135 MHz — Input + logic cell + output delays under 5.5 ns • Unparalleled FPGA performance for counters, data path, state machines,

architecture of cypress FLASH370 device

Abstract: architecture of cypress FLASH370 cpld FLASH370
Contextual Info: PRESS RELEASE CYPRESS CPLDs ADD IN-SYSTEM REPROGRAMMABILITY FLASH370i Devices Also Offer PCI Compliance, Bus-Hold Feature SAN JOSE, Calif., July 15, 1996 - Taking advantage of the outstanding routability and fixed timing model of its FLASH370 family of complex programmable logic devices

Contextual Info: PRESS RELEASE CYPRESS, QUICKLOGIC ANNOUNCE INTENT TO AMEND FPGA AGREEMENT All Cypress Resources To Be Redirected to High-Density ISR Product Development SAN JOSE, California.February 10, 1997  Cypress Semiconductor Corp. [CY:NYSE] and QuickLogic Corp. today announced their intent to terminate an existing

Contextual Info: CYPRESS Features • True 3.3V operation • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating Frequencies up to 85 MHz — Input + logic cell + output delays under 7 ns • Unparalleled FPGA performance for counters, data path, state machines,

Contextual Info: V CYPRESS Features • Full 3.3V operation • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz — Input + logic cell + output delays under 7 ns • Unparalleled FPGA performance for

Contextual Info: 7c33805: October 9, 1995 Revision: October 25, 1995 ADVANCED INFORMATION Ultra338005 UltraLogict Very High Speed 5K Gate 3.3V CMOS FPGA D Robust routing resources Features D Full 3.3V operation D Very high speed D D D D D D Ċ Loadable counter frequencies

IEEE1164

Abstract: 5-input-XOR schematic of TTL XOR Gates cy7c38003 3-input-XOR
Contextual Info: Ultra3800: October 13, 1995 Revision: October 25, 1995 PRELIMINARY Ċ Loadable counter frequencies greater than 185 MHz Ċ Data Path frequencies at greater than 200 MHz Ċ ChipĆtoĆchip operating frequencies up to 135 MHz Ċ Input + logic cell + output delays

Contextual Info: CYPRESS Features • Full 3.3V operation • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz — Input + logic cell + output delays under 7 ns • Unparalleled FPGA performance for counters, data path, state machines,