14L8 Search Results

12L10

Abstract: 16L6 20C1
Contextual Info: 2 4 -P in P A L / H A L D e v ice s 12L10 E ^7^ 3 E =E> 3 E = t> 3 E =E> 3 E =E> 3 E = 0 3 E :£ > 3 E = 0 3 E =E> 3 E = 0 3 E = I> 3 E 3 - - AND LOGIC nnnnv - - - - 1 20L2 14L8 E 3 d E E E E E E E E E E E AND LOGIC ARRAY ¡3 =L> 3 = 0 3 =L> IE =T> 3 = o 13

12L10

Abstract: 16L6 20C1
Contextual Info: 24-Pin P A L / H A L Devices 12L10 E ^7^ 3 E=E> 3 E= t> 3 E =E> 3 E - AND =E> 3 LOGIC = 0 3 E - nnnnv E:£ > 3 E = 0 3 E=E> 3 E= 0 3 E= I> 3 E 1 3 20L2 14L8 d E E E E E E E E E E E ¡3 3 3 AND LOGIC ARRAY 22] =L> 3 = 0 3 =L> IE =T> 3 = o 13 3 O ID AND LOGIC

12L10

Abstract: 16L6 20C1
Contextual Info: 2 4 -P in P A L / H A L D e v ice s 12L10 E ^7^ 3 E=E> 3 E= t> 3 E =E> 3 E - AND =E> 3 LOGIC = 0 3 E - nnnnv E:£ > 3 E = 0 3 E=E> 3 E= 0 3 E= I> 3 E 1 3 20L2 14L8 d E E E E E E E E E E E E 3 AND LOGIC ARRAY ¡3 =L> 3 = 0 3 =L> IE =T> 3 = o 13 3 O ID ¡3 1

12L10

Abstract: 16l6 14l8 Monolithic Memories pal18l4 islez 18L4 20C1 PAL12L10 PAL14L8 PAL16L6
Contextual Info: Small 24 Series 12L10, 14L8, 16L6, 18L4, 20L2, 20C1 Small 24 Series PAL12L10 14L8 PAL16L6 PAL18L4 PAL20L2 PAL20C1 INPUTS OUTPUTS POLARITY T rd ns Ice <mA) 12 14 16 18 20 20 10 8 6 4 2 2 LOW LOW LOW LOW LOW LOW 40 40 40 40 40 40 100 100 100 100 100 100

12L10

Abstract: 16L6 20C1 20X10
Contextual Info: 24-Pin PAL/HAL Devices 12L10 E ^7^ 3 E=E> 3 E=t> 3 E =E> 3 E - AND =E> 3 LOGIC = 0 3 E - nnnnv E:£ > 3 E = 0 3 E=E> 3 E= 0 3 E=I> 3 E 1 3 20L2 14L8 d E E E E E E E E E E E AND LOGIC ARRAY E 3 3 3 =L> 3 = 0 3 =L> IE =T> 3 = o 13 3 ID O AND LOGIC ARRAY 13 E

20L8B

Abstract: 12L10 16L6 20C1 id3-e
Contextual Info: 24-P in P A L /H A L Devices 12L10 E ^7^ 3 E=E> 3 E= t> 3 E =E> 3 E - AND =E> 3 LOGIC = 0 3 E - nnnnv E:£ > 3 E = 0 3 E=E> 3 E= 0 3 E = I> 3 E 1 3 20L2 14L8 d E E E E E E E E E E E 3 3 AND LOGIC ARRAY =L> 3 = 0 3 =L> IE =T> 3 = o 13 3 O ID AND LOGIC ARRAY

20l10

Abstract: 20X4 20C1 12L10 16L6
Contextual Info: 24-Pin PAL/HAL Devices 12L10 E ^7^ 3 E=E> 3 E=t> 3 E =E> 3 E - AND =E> 3 LOGIC = 0 3 E - nnnnv E:£ > 3 E = 0 3 E=E> 3 E= 0 3 E=I> 3 E 1 3 20L2 14L8 d E E E E E E E E E E E AND LOGIC ARRAY E 3 3 3 =L> 3 = 0 3 =L> IE =T> 3 = o 13 3 ID O AND LOGIC ARRAY 13 E

20x8

Abstract: 12L10 16L6 20C1
Contextual Info: 24-Pin PAL/HAL Devices 12L10 E ^7^ 3 E=E> 3 E=t> 3 E =E> 3 E - AND =E> 3 LOGIC = 0 3 E - nnnnv E:£ > 3 E = 0 3 E=E> 3 E= 0 3 E =I> 3 E 1 3 20L2 14L8 d E E E E E E E E E E E AND LOGIC ARRAY E 3 3 3 =L> 3 = 0 3 =L> IE =T> 3 = o 13 3 ID O S3 13 AND LOGIC ARRAY

12L10

Abstract: 16L6 20C1
Contextual Info: 2 4 -P in P A L / H A L D e v ice s 12L10 E ^7^ 3 E =E> 3 E = t> 3 E =E> 3 E =E> 3 E = 0 3 E :£ > 3 E = 0 3 E =E> 3 E = 0 3 E = I> 3 E 3 - - AND LOGIC nnnnv - - - - 1 20L2 14L8 d E E E E E E E E E E E AND LOGIC ARRAY E 3 3 3 =L> 3 = 0 3 =L> IE =T> 3 = o 13

12L10

Abstract: 16L6 20C1
Contextual Info: 24-Pin PAL/HAL Devices 12L10 E ^7^ 3 E=E> 3 E=t> 3 E =E> 3 E - AND =E> 3 LOGIC = 0 3 E - nnnnv E:£ > 3 E = 0 3 E=E> 3 E= 0 3 E=I> 3 E 1 3 20L2 14L8 d E E E E E E E E E E E AND LOGIC ARRAY E 3 3 3 =L> 3 = 0 3 =L> IE =T> 3 = o 13 3 ID O AND LOGIC ARRAY 13 E

12L10

Abstract: 16L6 20C1
Contextual Info: 2 4 -P in P A L /H A L Devices 12L10 E ^7^ 3 E=E> 3 E= t> 3 E =E> 3 E - AND =E> 3 LOGIC = 0 3 E - nnnnv E:£ > 3 E = 0 3 E=E> 3 E= 0 3 E= I> 3 E 1 3 20L2 14L8 d E E E E E E E E E E E AND LOGIC ARRAY E 3 3 3 =L> 3 = 0 3 =L> IE =T> 3 = o 13 3 O ID ¡3 22] AND

20l10

Abstract: 20L10A LT3973-3.3 20X4 12L10 16L6 20C1 20X4A LT3971-3.3
Contextual Info: 24-Pin PAL/HAL Devices 12L10 E ^7^ 3 E=E> 3 E= t> 3 E =E> 3 E - AND =E> 3 LOGIC = 0 3 E - nnnnv E:£ > 3 E = 0 3 E=E> 3 E= 0 3 E = I> 3 E 1 3 20L2 14L8 d E E E E E E E E E E E AND LOGIC ARRAY E 3 3 3 =L> 3 = 0 3 =L> IE =T> 3 = o 13 3 O ID AND LOGIC ARRAY 13

20L8A

Abstract: 20R4A 12L10 16L6 20C1
Contextual Info: 24-P in P A L /H A L Devices 12L10 E ^7^ 3 E=E> 3 E= t> 3 E =E> 3 E - AND =E> 3 LOGIC = 0 E - nnnnv 3 E:£ > 3 E = 0 3 E=E> 3 E= 0 3 E = I> 3 E 1 3 20L2 14L8 d E E E E E E E E E E E AND LOGIC ARRAY E 3 3 3 =L> 3 = 0 3 =L> IE =T> 3 = o 13 3 O ID AND LOGIC ARRAY

Contextual Info: Small 24 Series 12L10, 14L8, 16L6, 18L4, 20L2, 20C1 Small 24 Series PAL12L10 14L8 PAL16L6 PAL18L4 PAL20L2 PAL20C1 INPUTS O U T PU T S POLARITY TpD ns (mA) 12 14 16 18 20 20 10 8 6 4 2 2 LOW LOW LOW LOW LOW LOW 40 40 40 40 40 40 100 100 100 100 100 100

NEC 2561

Abstract: 2565 nec NEC 2562 nec 2565 GAL20V8 GAL20V8Z GAL20V8Z-12QJ GAL20V8Z-12QP GAL20V8Z-15QP GAL20V8ZD
Contextual Info: GAL20V8Z GAL20V8ZD Zero Power E2CMOS PLD Features Functional Block Diagram • ZERO POWER E2CMOS TECHNOLOGY — 100µA Standby Current — Input Transition Detection on GAL20V8Z — Dedicated Power-down Pin on GAL20V8ZD — Input and Output Latching During Power Down

20V8Q

Abstract: SL06 20V8H-15 20V8 GAL20V8 PAL20R8 PALCE20V8 PD3024 pal20v8
Contextual Info: COM'L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25, Q-20/25 PALCE20V8 Family EE CMOS 24-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS ◆ Pin and function compatible with all PAL 20V8 devices ◆ Electrically erasable CMOS technology provides reconfigurable logic and full testability

aeg diode Si 11 K

Abstract: aeg diode Si 11 aeg Diode D6 aeg diode Si 11 n
Contextual Info: ADV MICRO P LA / P L E / A R R AY S It D E | 02S75EL. OOSTMST Û T-46-13-47 Zero Power CMOS Hard Array Logic ZHAL 24A Series Features/Benefits Ordering information • Zero standby power PART NUM BER • Low power operation PACKAGE • High-speed C M O S technology

Contextual Info: Lattice GAL20LV8 Low Voltage E2CMOS PLD Generic Array Logic ; ; Semiconductor •■ Corporation Functional Block Diagram HIGH PERFORMANCE E2CMOS TECHNOLOGY — 3.5 ns Maximum Propagation Delay — Fmax = 250 MHz — 2.5 ns Maximum from Clock Input to Data Output

GAL Gate Array Logic

Abstract: GAL20V6
Contextual Info: GAL20V8 3 National Semiconductor GAL20V8 Generic Array Logic General Description The NSC E^CMOStm GAL device combines a high per­ formance CMOS process with electrically erasable floating gate technology. This programmable memory technology applied to array logic provides designers with reconfigurable

Contextual Info: Features Industry Standard Architecture - Emulates Many 24-Pin PALs - Low Cost Easy-to-Use Software Tools High-Speed Electrically Erasable Programmable Logic Devices - 7.5 ns Maximum Pin-to-Pin Delay Several Power Saving Options Device lcc, Stand-By lcc, Active

Contextual Info: Features Industry Standard Architecture - Emulates Many 24-pin PALs - Low-cost Easy-to-use Software Tools High-speed Electrically-erasable Programmable Logic Devices - 7.5 ns Maximum Pin-to-pin Delay Several Power Saving Options Device lcc, Standby lcc, Active

P20V8

Abstract: G20V8 GAL20V8B GAL20V8B-10LP GAL20V8B-15LPI IC of XOR GATE 20V8 GAL20V8 GAL20V8B-7LJ GAL20V8C
Contextual Info: GAL20V8 High Performance E2CMOS PLD Generic Array Logic Features Functional Block Diagram • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 5 ns Maximum Propagation Delay — Fmax = 166 MHz — 4 ns Maximum from Clock Input to Data Output — UltraMOS® Advanced CMOS Technology

Contextual Info: GAL20LV8ZD iüLattice Low Voltage, Zero Power E2CMOS PLD Generic Array Logic ! SS! ! SSemiconductor •■■■■■ Corporation Features • 3.3V LOW VOLTAGE, ZERO POWER OPERATION — JEDEC Com patible 3.3V Interface Standard — Interfaces with Standard 5V TTL Devices

Contextual Info: GAL20V8 Lattice High Performance E2CMOS PLD Generic Array Logic ; Semiconductor I Corporation Functional Block Diagram Features HIGH PERFORMANCE E2CMOS TECHNOLOGY — 5 ns Maximum Propagation Delay — Fmax = 1 6 6 MHz — 4 ns Maximum from Clock Input to Data Output