CY7C129 Search Results

CY7C1298A

Abstract: GVT7164C18
Contextual Info: 298A CY7C1298A/ GVT7164C18 64K x 18 Synchronous Burst RAM Pipelined Output Features • • • • • • • • • • • • • • • • • • • The CY7C1298A/GVT7164C18 SRAM integrates 65536x18 SRAM cells with advanced synchronous peripheral circuitry

CY7C1298H

Abstract: CY7C1298H-100AXC
Contextual Info: CY7C1298H 1-Mbit 64K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 64K x 18-bit common I/O architecture

CY7C1292DV18

Abstract: CY7C1294DV18
Contextual Info: CY7C1292DV18 CY7C1294DV18 9-Mbit QDR- II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports The CY7C1292DV18 and CY7C1294DV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate

Contextual Info: CY7C1292DV18 CY7C1294DV18 PRELIMINARY 9-Mbit QDR-II SRAM 2-Word Burst Architecture Features Configurations • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth • 2-Word Burst on all accesses

CY7C1299A

Contextual Info: 299A CY7C1299A 32K X 36 Dual I/O Dual Address Synchronous SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 100 and 83 MHz Fast Access Times: 5.0/6.0 ns Max. Single Clock Operation Single 3.3V –5% and +5% power supply VCC

waveforms of single port asynchronous read and w

Abstract: CY7C1299A
Contextual Info: CY7C1299A 32K x 36 Dual I/O Dual Address Synchronous SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 100 and 83 MHz Fast access times: 5.0/6.0 ns max. Single clock operation Single 3.3V –5% and +5% power supply VCC

CY7C1292DV18

Abstract: CY7C1294DV18
Contextual Info: CY7C1292DV18 CY7C1294DV18 9-Mbit QDR- II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports The CY7C1292DV18 and CY7C1294DV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate

CY7C1297H

Abstract: CY7C1297H-100AXC
Contextual Info: CY7C1297H 1-Mbit 64K x 18 Flow-Through Sync SRAM Functional Description[1] Features • 64K x 18 common I/O • 3.3V core power supply (VDD) • 2.5V/3.3V I/O power supply (VDDQ) • Fast clock-to-output times — 6.5 ns (for 133-MHz version) • Provide high-performance 2-1-1-1 access rate

Contextual Info: CY7C1297H PRELIMINARY 1-Mbit 64K x 18 Flow-Through Sync SRAM Functional Description[1] Features • 64K x 18 common I/O • 3.3V –5% and +10% core power supply (VDD) • 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version)

CY7C1297A

Abstract: GVT7164B18
Contextual Info: 297A CY7C1297A/ GVT7164B18 64K X 18 Synchronous Burst SRAM Features • • • • • • • • • • • • • • • • • Fast access times: 9 and 10 ns Fast clock speed: 66 and 50 MHz Provide high performance 2-1-1-1 access rate Fast OE access times: 5 and 6 ns

CY7C1297H

Abstract: CY7C1297H-133AXC
Contextual Info: CY7C1297H 1-Mbit 64K x 18 Flow-Through Sync SRAM Functional Description[1] Features • 64K x 18 common I/O • 3.3V core power supply (VDD) • 2.5V/3.3V I/O power supply (VDDQ) • Fast clock-to-output times — 6.5 ns (for 133-MHz version) • Provide high-performance 2-1-1-1 access rate

A101

Abstract: CY7C1297F CY7C1297F-117AC
Contextual Info: CY7C1297F 1-Mbit 64K x 18 Flow-Through Sync SRAM Features • 64K x 18 common I/O • 3.3V –5% and +10% core power supply (VDD) • 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version) — 7.5 ns (117-MHz version) • Provide high-performance 2-1-1-1 access rate

BV25

Abstract: CY7C129 CY7C130 CY7C131 CY7C132 EV25 ev18
Contextual Info: CY7C129*DV18/CY7C130*DV25 CY7C130*BV18/CY7C130*BV25/CY7C132*BV25 CY7C131*BV18 / CY7C132*BV18/CY7C139*BV18 CY7C191*BV18/CY7C141*AV18 / CY7C142*AV18/ CY7C151*V18 /CY7C152*V18 Errata Revision: *D March 04, 2008 RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata This document describes the DOFF issue for QDRII/DDRII, the Output Buffer, the JTAG and the DLL issue for

CY7C1297H

Abstract: CY7C1297H-100AXC
Contextual Info: CY7C1297H 1-Mbit 64K x 18 Flow-Through Sync SRAM Functional Description[1] Features • 64K x 18 common I/O • 3.3V core power supply (VDD) • 2.5V/3.3V I/O power supply (VDDQ) • Fast clock-to-output times — 6.5 ns (for 133-MHz version) • Provide high-performance 2-1-1-1 access rate

Contextual Info: CY7C1298F 1-Mb 64K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 64K x 18-bit common I/O architecture

112434

Abstract: CY7C1297A GVT7164B18
Contextual Info: 297A CY7C1297A/ GVT7164B18 64K X 18 Synchronous Burst SRAM Features • • • • • • • • • • • • • • • • • Fast access times: 9 and 10 ns Fast clock speed: 66 and 50 MHz Provide high performance 2-1-1-1 access rate Fast OE access times: 5 and 6 ns

A101

Abstract: CY7C1298F CY7C1298F-133AC
Contextual Info: CY7C1298F 1-Mbit 64K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 64K x 18-bit common I/O architecture

05564

Abstract: BV25 CY7C129 CY7C130 CY7C131 CY7C132 CY7C1422AV18 1428A
Contextual Info: CY7C129*DV18/CY7C130*DV25 CY7C130*BV18/CY7C130*BV25/CY7C132*BV25 CY7C131*BV18 / CY7C132*BV18/CY7C139*BV18 CY7C191*BV18/CY7C141*AV18 / CY7C142*AV18/ CY7C151*V18 /CY7C152*V18 Errata Revision: *C May 02, 2007 RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata This document describes the DOFF issue for QDRII/DDRII and the Output Buffer and JTAG issues for

Contextual Info: CY7C1298H 1-Mbit 64K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 64K x 18-bit common I/O architecture

CY7C1299A

Abstract: CE2Y 126-196
Contextual Info: CY7C1299A 32K x 36 Dual I/O Dual Address Synchronous SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 100 and 83 MHz Fast access times: 5.0/6.0 ns max. Single clock operation Single 3.3V –5% and +5% power supply VCC

Contextual Info: THIS SPEC IS OBSOLETE Spec No: 001-00350 Spec Title: CY7C1292DV18/CY7C1294DV18 9-Mbit QDR II SRAM 2-Word Burst Architecture Sunset Owner: AJU Replaced By: None CY7C1292DV18 CY7C1294DV18 9-Mbit QDR® II SRAM 2-Word Burst Architecture Features Configurations

CY7C1298A

Abstract: GVT7164C18
Contextual Info: 298A CY7C1298A/ GVT7164C18 64K x 18 Synchronous Burst RAM Pipelined Output Features • • • • • • • • • • • • • • • • • • • The CY7C1298A/GVT7164C18 SRAM integrates 65536x18 SRAM cells with advanced synchronous peripheral circuitry

A101

Abstract: CY7C1298F CY7C1298F-133AC
Contextual Info: CY7C1298F 1-Mbit 64K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 64K x 18-bit common I/O architecture

ay-13

Abstract: CY7C1299A
Contextual Info: CY7C1299A 32K x 36 Dual I/O Dual Address Synchronous SRAM Features • • • • • • • Fast clock speed: 100 and 83 MHz Fast access times: 5.0/6.0 ns max. Single clock operation Single 3.3V –5% and +5% power supply VCC Separate VCCQ for output buffer