DQ116 Search Results

DG123

Abstract: DG125 Dtl 937 DG118
Contextual Info: g { f iü i DQ116111811231125 4 and 5-Channel Drlver-MOS-FET Switch Combinations M ilitary Series - 5 5 ° C t o + 12 5°C FEATURES GENERAL DESCRIPTION • This series includes devices w ith fo u r and five channel sw itching cap ability. Each channel is composed o f a driver

EDI4164MEV50SM

Abstract: EDI4164MEV-RP EDI4164MEV60SM EDI4164MEV70SM 4mx16 edo EDI4164MEV50SI
Contextual Info: EDI4164MEV-RP HI-RELIABILITY PRODUCT 4Mx16 EDO Extended Data Out Dynamic RAM 3.3V FEATURES • 4 Meg x 16 bit CMOS Dynamic RAM ■ RAS - Only, CAS-before-RAS, and HIDDEN refresh capability ■ Package: ■ Low Operating Power Dissipation ■ Access Time: 50, 60 and 70ns

DQ111

Abstract: DQ139 DQ131
Contextual Info: UGSN7004A8HHF-256 Data sheets can be downloaded at www.unigen.com 256MB 8M x 144 2PCS FPM MODE DRAM MODULE FPM Mode buffered DIMM With ECC based on 18 pcs 8M x 8 DRAM with LVTTL, 8K Refresh 256MB 200pin DIMM (2PCS 128MB (8M x 144) module kit) FEATURES Single 5.0V ± 10% power supply

DQ111

Contextual Info: SM544083U74S6UU June 6, 2000 Revision History • June 9, 2000 Added Command Truth Table, Mode Register Table and notes. Modified waveforms Auto Refresh (CBR cycle and Power Down Mode and Clock Mask). • March 24, 1999 Datasheet released. Corporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com

Contextual Info: SM544028002BXGU September 1996 Rev 0 SMART Modular Technologies SM544028002BXGU 32MByte 2M x 144 CMOS DRAM Module - Buffered General Description Features The SM544028002BXGU is a high performance, 32-megabyte dynamic RAM module organized as 2M words by 144 bits, in a 100-pin, dual readout, leadless,

GS841E18A

Abstract: GS841E18AT-180 256k x 18 119bga TS/103/02 B180
Contextual Info: GS841E18AT/B-180/166/150/130/100 180 MHz–100 MHz 3.3 V VDD 3.3 V and 2.5 V I/O 256K x 18 Sync Cache Tag TQFP, BGA Commercial Temp Industrial Temp Features • 3.3 V +10%/–5% core power supply, 2.5 V or 3.3 V I/O supply • Dual Cycle Deselect DCD • Intergrated data comparator for Tag RAM application

BA5 marking

Abstract: DQ112-127 BA7 marking HMD4M144D9WG DQ113 BA6 marking BA6137 DQ99
Contextual Info: HANBit HMD4M144D9WG 64Mbyte 4Mx144 200-pin ECC Mode 4K Ref. DIMM Design 5V Part No. HMD4M144D9WG GENERAL DESCRIPTION The HMD4M144D9WG is a 4Mbit x 144bit dynamic RAM high-density memory module. The module consists of eight CMOS 4Mx16bit DRAMs in 50-pin TSOP packages and one CMOS 4M x 16bit DRAM in 50pin TSOP package

GS84118-2000207

Abstract: DQ116
Contextual Info: GS84118T/B-166/150/133/100 166 MHz–100 MHz 8.5 ns–12 ns 3.3 V VDD 3.3 V and 2.5 V I/O 256K x 18 Sync Cache Tag TQFP, BGA Commercial Temp Industrial Temp Features • 3.3 V +10%/–5% core power supply, 2.5 V or 3.3 V I/O supply • Intergrated data comparator for Tag RAM application

Contextual Info: PRELIMINARY M IC R O N ‘ » Eg R>4'n' DRAM MT4LC4M16R6 FEATURES • Single +3.3V +0.3V pow er supply • Industry-standard xl6 pinout, timing, functions and package • 12 row, 10 colum n addresses • High-performance CMOS silicon-gate process • All inputs, outputs and clocks are LVTTL-compatible

PBSRAM

Abstract: MC8031
Contextual Info: M C80364K32, MC8031 28K32 6 4 K X 3 2 , 1 2 8 K X 3 2 PIPELINE BURST S R A M M o Sys 6 - - • High performance, low power pipeline burst SRAM

Contextual Info: 1, 2 MEG x 64 DRAM SODIMMs TECHNOLOGY, INC. MT4LDT164H X (S) MT8LDT264H(X)(S) SMALL-OUTLINE DRAM MODULE FEATURES PIN ASSIGNMENT (Front View) 144-Pin Small-Outline DIMM (DF-7) 1 Meg x 64 (shown), (DF-8) 2 Meg x 64 • JEDEC- and industry-standard pinout in a 144-pin,

Contextual Info: MITSUBISHI LSIs M5M564R16CJ.TP-10,-12,-15 í f at Nc*,ce » • uSume Pdid 1048576-BIT 65536-WORD BY 16-BIT CMOS STATIC RAM DESCRIPTION The M5M564R16C is a family of 65536-word by 16-bit static RAMs, fabricated with the high performance CMOS process and

Contextual Info: 9 Jul ,1997 MITSUBISHI LSIs M5M51016BTP,RT-12VL-I, -12VLL-I 1048576-BIT 65536-WQRD BY 16-BIT CMOS STATIC RAM DESCRIPTION T h e M 5 M 5 1 0 1 6 B T P , R T a re a 1 0 4 8 5 7 6 -b it C M O S s ta tic RAM o rg a n ize d a s 6 5 5 3 6 w o rd b y 1 6-b it w h ich a re fa b ric a te d u sing

MT4LC4M16R6

Abstract: MT4LC4M16R6TG5 MT4LC4M16R6TG-5
Contextual Info: PRELIMINARY 4 MEG x 16 EDO DRAM TECHNOLOGY, INC. MT4LC4M16R6 DRAM FEATURES • Single +3.3V ±0.3V power supply • Industry-standard x16 pinout, timing, functions and package • 12 row, 10 column addresses • High-performance CMOS silicon-gate process • All inputs, outputs and clocks are LVTTL-compatible

DQ124

Abstract: DQ77 DQ100 DQ99 DQ87 DQ88 DQ111 DQ106 DQ72 DQ79
Contextual Info: UG016E14488HSG Data sheets can be downloaded at www.unigen.com 256M Bytes 16M x 144 bits EDO MODE DRAM MODULE EDO Mode buffered DIMM With ECC based on 36 pcs 8M x 8 DRAM with LVTTL, 8K Refresh PIN ASSIGNMENT (Front View) 200-Pin DIMM FEATURES 256MB (16 Meg x 144)

DQ112

Abstract: UG016C14488HSG-6 DQ100 DQ88
Contextual Info: UG016C14488HSG Data sheets can be downloaded at www.unigen.com 256M Bytes 16M x 144 bits FPM MODE DRAM MODULE FPM Mode buffered DIMM With ECC based on 36 pcs 8M x 8 DRAM with LVTTL, 8K Refresh PIN ASSIGNMENT (Front View) 200-Pin DIMM FEATURES 256MB (16 Meg x 144)

Contextual Info: 9 J u l ,1997 MITSUBISHI LSIs M5M51016BTP, RT-12VL, -12VLL 1048576-BIT 65536-WQRD BY 16-BIT CMOS STATIC RAM DESCRIPTION The M5M51016BTP, RT are a 1048576-bit CMOS static RAM organized as 65536 word by 16-bit which are fabricated using high-performance triple polysilicon CMOS technology. The use of

Contextual Info: MITSUBISHI LSIs M5M51016BTP,RT-1 OVL-I, -10VLL-I 1048576-BIT 65536-WQRD BY 16-BIT CMOS STATIC RAM DESCRIPTION The M5M51016BTP, RT are a 1048576-bit CMOS static RAM organized as 65536 word by 16-bit which are fabricated using high-performance triple polysilicon CMOS technology. The use of

W78M32VP

Abstract: W78M64VP-XBX x0355
Contextual Info: White Electronic Designs W78M64VP-XBX *ADVANCED 8Mx32 Flash 3.3V Page Mode Multi-Chip Package FEATURES Access Times of 110, 120ns Secured Silicon Sector region Packaging Page Mode • 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random

Contextual Info: UG08E14488HSG-6 128M Bytes 8M x 144 DRAM 200Pin DIMM w/ECC based on 8M x 8 General Description Features The U08E14488HSG-6 is a 8M x 144 200pin DIMM. The module is organized as a 8M x 144 high speed memory array and optimized for use in ECC applications. This module consist of 18 pcs 8M x 8

Contextual Info: ADVANCE MT4LC4M16N3/R6 4 MEG X 16 DRAM l^ iic n g N 4 M E G X 16 D R A M S DRAM 3.3V, EDO PAGE MODE PIN ASSIGNMENT Top View • Single +3.3V +0.3V power supply • Industry-standard x l6 pinout, timing, functions and package • 13 row-addresses, 9 column-addresses (N3) or

Contextual Info: KM416C256LL CMOS DRAM 256Kx 16 Bit CMOS Dynamic RAM with Fast Page Mode FEATURES GENERAL DESCRIPTION • Performance range: The Samsung KM416C256LL is a CMOS high speed 262,144 bit x 16 Dynamic Random Access Memory. Its design is optimized for high performance applications

sht22

Abstract: SHT12 5BE1 EL114 6nc3 SHT20 RAM128KX8 SHT13 VG-468 57BE2
Contextual Info: 5 EBSA-110 SHEET SIG 4 Schematic PREFIXES 3 2 BAN#=EBSA-110 REV#=REVB Directory 1 - STRONGARM SHT20, C 1 - Schematic sht 2 - Block sht 3 CPU_, sht 4 - Debug sht 5 - SSRAM sht 6 BUF_, IO_ Address sht 7 MUX_, SIM_ DRAM sht 8 CTA_, CTB_ Control sht 9 CTA_, CTB_

B180

Contextual Info: GS841E18AT/B-180/166/150/130/100 TQFP, BGA Commercial Temp Industrial Temp 180 MHz–100 MHz 3.3 V VDD 3.3 V and 2.5 V I/O 256K x 18 Sync Cache Tag Features • 3.3 V +10%/–5% core power supply, 2.5 V or 3.3 V I/O supply • Dual Cycle Deselect DCD • Intergrated data comparator for Tag RAM application